scholarly journals Low power synthesis for asynchronous FIFO using unified power format (UPF)

2018 ◽  
Vol 7 (2.8) ◽  
pp. 7
Author(s):  
Avinash Yadlapati ◽  
K Hari Kishore
Keyword(s):  
Low Power ◽  
Logic Synthesis ◽  
Reducing Power ◽  
Low Power Design ◽  
Design Flow ◽  
Functional Verification ◽  
Design For Test ◽  
Asic Design ◽  
The Common ◽  
Low Power Synthesis

Low power Design is the challenge for the current SoC Designers. With the growing complexity of the chips and the shrinking technology, power consumption in ASIC’s has become a major challenge for the ASIC Engineer. The low power challenge is at every level of the ASIC Design flow. The low power techniques are applies at the Micro architecture level, RTL Design Level, Functional Verification level, Logic Synthesis level, Design for Test level, and Physical Design level. Nowadays, with the complexity gradually increasing at the SoC level, some of the EDA companies like Synopsys and Cadence are integrating the low power techniques in the tool itself. For instance, the two most commonly used low power flows are Unified Power Format (UPF) and Common Power Format (CPF). The Unified power format is from Synopsys flow while the Common Power format is from Cadence flow. In this paper, the emphasis is on reducing power by taking an Asynchronous FIFO with two separate clocks and applying the Unified power format flow in it. This paper presents the results of the research reported by the Synopsys Design Compiler before applying the UPF flow and after applying the UPF flow.

scholarly journals Design of Power Efficient 32-Bit Processing Unit

2018 ◽  
Vol 7 (2.16) ◽  
pp. 52
Author(s):  
Dharmavaram Asha Devi ◽  
Chintala Sandeep ◽  
Sai Sugun L
Keyword(s):  
Low Power ◽  
System Design ◽  
Power Analysis ◽  
Low Power Design ◽  
Design Flow ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Front End ◽  
Verification Process

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.  

Synopsys Low-Power Design Flow

2005 ◽  
pp. 1-20
Author(s):  
Renu Mehra ◽  
Barry Pangrle
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Design Flow

scholarly journals The Importance of Energy Efficiency in Engineering and Informatics

2021 ◽  
Vol 2 (2) ◽  
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Digital Circuits ◽  
Reducing Power ◽  
Digital Filtering ◽  
Low Power Design ◽  
Engineering Systems ◽  
Algorithmic Approach ◽  
Modern Engineering ◽  
Power Frequency

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.

scholarly journals The Importance of Energy Efficiency in Engineering and Informatics

2021 ◽  
Vol 2 (2) ◽  
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Digital Circuits ◽  
Reducing Power ◽  
Digital Filtering ◽  
Low Power Design ◽  
Engineering Systems ◽  
Algorithmic Approach ◽  
Modern Engineering ◽  
Power Frequency

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

Low Power Considerations in Ubiquitous Computing

2010 ◽  
pp. 158-174
Author(s):  
Robert Tesch ◽  
Ashok Kumar ◽  
Jamie Mason ◽  
Dania Alvarez ◽  
Mario Di’Mattia ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ubiquitous Computing ◽  
Reducing Power ◽  
Low Power Design ◽  
Power Budget ◽  
Computing Systems ◽  
Research Directions ◽  
Design Considerations ◽  
Battery Technology

Majority of the devices that are used in ubiquitous computing are expected to be as small as possible, be able to perform as many computations as possible, and transmit the results to another device or computer. Such expectations in performance put a pressure on the power budget of such devices. It is a well-known fact that the advances in battery technology are much slower and cannot keep up with the performance demands of tiny gadgets unless new methods of designing and managing hardware and software are developed and used. This chapter will introduce the motivation for low power design considerations by discussing the power limitations of ubiquitous computing devices. Then the chapter will discuss the research directions that are being pursued in literature for reducing power consumption and increasing efficiency of ubiquitous computing systems.

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format

2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Power ◽  
Low Power Design ◽  
Design Strategy ◽  
Design Flow ◽  
Battery Life ◽  
Electronic Systems ◽  
High Power Consumption

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.

scholarly journals Fault-tolerant ASIC: Design and implementation

2013 ◽  
Vol 26 (3) ◽  
pp. 175-186 ◽  
Author(s):  
Z. Stamenkovic ◽  
V. Petrovic ◽  
G. Schoof
Keyword(s):  
Fault Tolerant ◽  
Logic Synthesis ◽  
Design Flow ◽  
Single Event ◽  
Asic Design ◽  
Single Event Upsets ◽  
Design And Implementation ◽  
Standard Design ◽  
Extra Step ◽  
Definition Of

The paper presents fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for a modified fault-tolerant ASIC design flow. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the redundant power domains and placement of the SPS) have to be performed in the layout phase. The concept has been proven by design and implementation of the two digital circuits: shift-register and synchronous counter.

Low power design flow based on Unified Power Format and Synopsys tool chain

2013 ◽  
Author(s):  
V. Gourisetty ◽  
H. Mahmoodi ◽  
V. Melikyan ◽  
E. Babayan ◽  
R. Goldman ◽  
...  
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Design Flow ◽  
Tool Chain
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