Using Explainable Artificial Intelligence to Improve Process Quality: Evidence from Semiconductor Manufacturing

We develop a data-driven decision model to improve process quality in manufacturing. A challenge for traditional methods in quality management is to handle high-dimensional and nonlinear manufacturing data. We address this challenge by adapting explainable artificial intelligence to the context of quality management. Specifically, we propose the use of nonlinear modeling with Shapley additive explanations to infer how a set of production parameters and the process quality of a manufacturing system are related. Thereby, we contribute a measure of process importance based on which manufacturers can prioritize processes for quality improvement. Grounded in quality management theory, our decision model selects improvement actions that target the sources of quality variation. The decision model is validated in a real-world application at a leading manufacturer of high-power semiconductors. Seeking to improve production yield, we apply our decision model to select improvement actions for a transistor chip product. We then conduct a field experiment to confirm the effectiveness of the improvement actions. Compared with the average yield in our sample, the experiment returns a reduction in yield loss of 21.7%. Furthermore, we report on results from a postexperimental rollout of the decision model, which also resulted in significant yield improvements. We demonstrate the operational value of explainable artificial intelligence by showing that critical drivers of process quality can go undiscovered by the use of traditional methods. This paper was accepted by Charles Corbett, operations management.

Matryoshka phonon twinning in α-GaN

Understanding lattice dynamics is crucial for effective thermal management in electronic devices because phonons dominate thermal transport in most semiconductors. α-GaN has become a focus of interest as one of the most important third-generation power semiconductors, however, the knowledge on its phonon dynamics remains limited. Here we show a Matryoshka phonon dispersion of α-GaN with the complementary inelastic X-ray and neutron scattering techniques and the first-principles calculations. Such Matryoshka twinning throughout the basal plane of the reciprocal space is demonstrated to amplify the anharmonicity of the related phonons through creating abundant three-phonon scattering channels and cutting the lifetime of affected modes by more than 50%. Such phonon topology contributes to reducing the in-plane thermal transport, thus the anisotropic thermal conductivity of α-GaN. The results not only have implications for engineering the thermal performance of α-GaN, but also offer valuable insights on the role of anomalous phonon topology in thermal transport of other technically semiconductors.

Load-Independent Voltage Balancing of Multi-Level Flying Capacitor Converters in Quasi-2-Level Operation

Quasi-2-level (Q2L) operation of multi-level bridge-legs, especially of flying-capacitor converters (FCC), is an interesting option for realizing single-cell power conversion in applications whose system voltages exceed the ratings of available power semiconductors. To ensure equal voltage sharing among a Q2L-FCC’s switches, the voltages of a Q2L-FCC’s minimized flying capacitors (FCs) must always be balanced. Thus, we propose a concept for load-independent FC voltage balancing: For non-zero load current, we use a model predictive control (MPC) approach to identify the commutation sequence of the individual switches within a Q2L transition that minimizes the FC or cell voltage errors. In case of zero load current, we employ a novel MPC-based approach using cell multiple switching (CMS), i.e., the insertion of additional zero-current commutations within a Q2L transition, to exchange charge between the FCs via the charging currents of the switches’ parasitic capacitances. Experiments with a 5-level FCC half-bridge demonstrator confirm the validity of the derived models and verify the performance of the proposed load-independent balancing concept.

High energy-efficient electrical drive with multilevel inverter and widebandgap power semiconductors

Multilevel inverters are an alternative for electrical drives with DC link voltage between 560 and 750 V. In this voltage range new wide-bandgap power switches (SiC MOSFET, GaN FET) are available. The paper analyses three-, four-, five- and seven-level inverters. A simulation model of the drive system, including the 11 kW induction motor and motor filter is developed. By replacing IGBTs with SiC FETs, the twolevel inverter achieved a loss reduction of 59 % at 25 °C and 150 °C at nominal motor operation point. By using the five-level inverter with GaN FETs, a further loss reduction of 9 % only at low junction temperature is possible. With a higher number of inverter levels, the size of the motor filter can be reduced. With five inverter levels and 40 kHz switching frequency volume and weight can be reduced by 86 % and 78 % respectively. The overall efficiency of the drive system achieves 98.5 % at 25 °C and 98.1 % at 150 °C. Compared to the state of the art (two-level with IGBTs with 5 kHz), this is an improvement of 2.1 % at 25 °C and 2.7 % at 150 °C.

Protection of Power Semiconductors in Inverters, using Fuses and their Coordination with the Protection Schemes of the Distribution System

The integration of Distributed Energy Resources (DER) implies an important challenge for the protection of the distribution network, due to the incorporation of devices with less capacity to withstand normal disturbances in distribution systems, particularly for overcurrents and overvoltages. The increasingly widespread use of power electronics, incorporated in rectifiers and inverters, which due to its weakness requires highspeed protection devices, complicates coordination with the traditional protection of distribution systems. Converters (rectifiers and inverters) require ultra-fast protection against high current faults, conditions that currently only meet high breaking capacity fuses. The response characteristics of these ultra-fast fuses, oblige the professional in charge of the protection of the distribution system to have a deep knowledge about the behavior of the power electronics in the face of overcurrents, and to know also how the fuses, through the selection of its rated values and characteristic curves protects it. Coordination of the rating values and characteristics of these fuses with their counterparts (when they exist) of traditional protection devices is the main objective of this article. Particular terms are explained in detail, such as fault current asymmetry and its effect on the coordination of protections, specific energy, etc. It is concluded that deep knowledge of the dissimilar characteristics of power electronics devices and the usual devices of distribution networks, with regard to their protections, are essential to obtain a maximum use of the traditional scheme with the addition of DER.

Cascaded Smart Gate Drivers for Modular Multilevel Converters Control: A Decentralized Voltage Balancing Algorithm

Recent Modular Multilevel Converter (MMC) topology allows for drastic improvements in power electronic conversion such as higher energy quality, lower power semiconductors electrical stress, decreased Electro-Magnetic Interferences (EMI), and reduced switching losses. MMC is widely used in High Voltage Direct-Current (HVDC) transmissions as it offers, theoretically, no voltage limit. However, its control electronic structure is not modular itself. Especially, the insulation voltage between the submodule gate drivers’ primaries and secondaries depends on the number of submodules. The converter voltage levels cannot be increased without designing all gate driver isolations again. To solve that issue, the novel concept of distributed galvanic insulation is introduced for multilevel converters. The submodule’s gate drivers are daisy-chained, which naturally reduces the insulation voltage to the submodule capacitor voltage, regardless of the number of submodules. The MMC becomes truly modular as the number of submodules can be increased without impacting on the previous control electronic circuit. Such an innovative control structure weakens the link between the main control unit and the gate drivers. This inherent structural problem can be solved through the use of Smart-Gate Drivers (SGD), as they are often equipped with fast and bidirectional communication channels, while highly increasing the converter reliability. The innovation proposed in that work is the involvement of smart gate drivers in the distributed galvanic insulation-based MMC control and monitoring. First, the numerous benefits of smart gate drivers are discussed. Then, an innovative Voltage Balancing Algorithm directly integrated on the chained gate drivers is proposed and detailed. It features a tunable parameter, offering a trade-off between accurate voltage balancing and execution time. The proposed embedded algorithm features a low execution time due to simultaneous voltage comparisons. Such an algorithm is executed by the gate drivers themselves, relieving the main control unit in an original decentralized control scheme. A simulation model of a multi-megawatts three-phase grid-tied MMC inverter is realized, allowing validation of the proposed algorithm. Matlab/Simulink logic blocs allow us to simulate a typical CPLD/FPGA component, often embedded on smart gate drivers. The converter with the proposed embedded algorithm is simulated in steady-state and during load impact. The controlled delay and slew rate inferred by the algorithm do not disturb the converter behavior, allowing its conceptual validation.