A 1.5-b Front-end Sub-ADC with Symmetrical Cross Coupled Bootstrap and Adaptive Power/Ground Switches for GS/s Sampling Rate SHA-less Pipeline ADCs

Author(s):  
Hakan Cetinkaya ◽  
Tufan Cockun Karalar
Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7335
Author(s):  
Jose Manuel Valero-Sarmiento ◽  
Parvez Ahmmed ◽  
Alper Bozkurt

Photoplethysmography is an extensively-used, portable, and noninvasive technique for measuring vital parameters such as heart rate, respiration rate, and blood pressure. The deployment of this technology in veterinary medicine has been hindered by the challenges in effective transmission of light presented by the thick layer of skin and fur of the animal. We propose an injectable capsule system to circumvent these limitations by accessing the subcutaneous tissue to enable reliable signal acquisition even with lower light brightness. In addition to the reduction of power usage, the injection of the capsule offers a less invasive alternative to surgical implantation. Our current prototype combines two application-specific integrated circuits (ASICs) with a microcontroller and interfaces with a commercial light emitting diode (LED) and photodetector pair. These ASICs implement a signal-conditioning analog front end circuit and a frequency-shift keying (FSK) transmitter respectively. The small footprint of the ASICs is the key in the integration of the complete system inside a 40-mm long glass tube with an inner diameter of 4 mm, which enables its injection using a custom syringe similar to the ones used with microchip implants for animal identification. The recorded data is transferred wirelessly to a computer for post-processing by means of the integrated FSK transmitter and a software-defined radio. Our optimized LED duty cycle of 0.4% at a sampling rate of 200 Hz minimizes the contribution of the LED driver (only 0.8 mW including the front-end circuitry) to the total power consumption of the system. This will allow longer recording periods between the charging cycles of the batteries, which is critical given the very limited space inside the capsule. In this work, we demonstrate the wireless operation of the injectable system with a human subject holding the sensor between the fingers and the in vivo functionality of the subcutaneous sensing on a pilot study performed on anesthetized rat subjects.


2014 ◽  
Vol 687-691 ◽  
pp. 3285-3288
Author(s):  
Ai Guo ◽  
Rong Bin Hu

A capacitor memory erasing technique for pipeline ADC is introduced, which insert a clearing phase to the traditional working timing sequence of the MDAC to erasing the residual charges on the sampling capacitor. The measurement shows that the 14-bit pipeline ADC adopting the proposed technique can achieve a sampling rate of 250MSPS with SNR 69dB, SFDR 80dB, compared with the traditional ADC of sampling rate 100MSPS, SNR 60dB, SFDR 71dB, which proves the proposed technique can improve the performances of pipeline ADCS obviously.


2011 ◽  
Vol 2011 ◽  
pp. 1-11
Author(s):  
Yuan Yu ◽  
Qing Chang ◽  
Yuan Chen

In the near future, RF front-ends of GNSS receivers may become very complicated when multifrequency signals are available from at least four global navigation systems. Based on the direct RF sampling technique, fully digitized receiver front-ends may solve the problem. In this paper, a direct digitization RF front-end scheme is presented. At first, a simplified sampling rate selection method is adopted to determine the optimal value. Then, the entire spectrum of GNSS signal is directly digitized through RF sampling at a very fast sampling rate. After that, the decimation and filtering network is designed to lower the sampling rate efficiently. It also realizes the digital downconversion of the signal of interest and the separation of narrow band signals from different navigation systems. The scheme can be flexibly implemented in software. Its effectiveness is proved through the experiment using simulated and true signals.


2014 ◽  
Vol 602-605 ◽  
pp. 2744-2747
Author(s):  
Ting Li ◽  
Yong Zhang ◽  
Yan Wang ◽  
Lu Liu ◽  
Xu Wang

In this paper, a 16 bit 250MSPS pipelined ADC is presented. To alleviate noise induced by mismatching of the MDAC sampling network and comparator sampling network, scaling network structure is applied; to implement high-speed sampling, a high-efficient front-end circuit structure is presented; to further improve the sampling rate, a double duty cycle clock circuit is presented; to improve the linearity of the ADC, the sample and hold circuit is removed and the improved clock controlled boost circuit is used. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 0.18um CMOS process.


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