chip carrier
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HardwareX ◽  
2021 ◽  
pp. e00245
Author(s):  
Federico Cantoni ◽  
Gabriel Werr ◽  
Laurent Barbe ◽  
Ana Maria Porras ◽  
Maria Tenje

2019 ◽  
Vol 187 ◽  
pp. 106217 ◽  
Author(s):  
Ngo Van He ◽  
Keisuke Mizutani ◽  
Yoshiho Ikeda

2018 ◽  
Vol 123 (12) ◽  
pp. 125703 ◽  
Author(s):  
J. Rieprich ◽  
M. Winterfeldt ◽  
R. Kernke ◽  
J. W. Tomm ◽  
P. Crump

Author(s):  
Leandro Muela ◽  
Raj Kabadi ◽  
Eric Barbian

Abstract A novel approach for solid immersion lens (SIL) assisted imaging and backside analysis of chip-on-board devices is presented. The procedure relies on complete die extraction from its original package, and repackage into a FA-friendly Plastic Quad-Flat Package (PQFP) chip carrier with inverted mold configuration, which enables access to the backside of the die through grinding/polishing or other methods. This procedure also relies on complementing use of device-specific DUT boards with generic arrangement of I/O, ground and power domains, coupled with a bench-test board equipped with the same pin-out configuration and a custom carrier built specifically for these DUT boards. This generic approach broadens the use of this solution to an entire family of devices and offers a balance of test capability leading to fault localization success and cost control.


2016 ◽  
Vol 2016 (NOR) ◽  
pp. 1-6 ◽  
Author(s):  
Jakob Gakkestad ◽  
Ottar Opland ◽  
Per Dalsjø ◽  
Susanne Helland ◽  
Helge Kristiansen ◽  
...  

Polymer Core Solder Balls (PCSB) have been used as interconnects between a 16 pin leadless chip carrier (LCC) ceramic package and a small FR4 board. A comparison was made between two different volumes of SnPb solder and an isotropic conductive adhesive (ICA) for the attachment of the PCSB to the board and to the package. Shear testing and electrical measurements were performed to characterize the interconnects as bonded and during thermal shock cycling (TSC) tests. No significant reductions of the measured fracture forces was observed for any of the sample groups. However, using a larger volume of solder or ICA resulted in less degradation of interconnect resistance during TSC, and the results for the solder were overall better than for ICA.


2016 ◽  
Vol 13 (1) ◽  
pp. 23-32 ◽  
Author(s):  
Hao Zhang ◽  
Simon S. Ang

With the emergence of new power semiconductor devices and packaging technologies, the power density of the power packages or modules is increasing rapidly. Double-sided cooling power packages maximize heat dissipation by enabling heat removal from both the top and bottom sides of the module. This article compares single-sided and double-sided cooling power packaging structures to elucidate advantages and disadvantages of these packaging structures in terms of thermal and thermo-mechanical based on finite element simulations. Simulation results reveal that double-sided cooling power packages greatly improve their thermal performances, but they face challenges due to their high thermo-mechanical stresses. The use of a viscoelastic underfill resin and a coefficient of thermal expansion–matched ceramic chip carrier in the double-sided cooling power packaging structure is shown to reduce thermo-mechanical stresses.


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