Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics

In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown with the thickness of each SiGe layer less than 10 nm is realized on a Si substrate without any structural defect impact by optimizing its epitaxial grown process. Meanwhile, the Ge atomic fraction of the SiGe layers is very uniform and its SiGe/Si interfaces are sharp. Then, a vertical profile of the stacked SiGe/Si Fin is achieved with HBr/O2/He plasma by optimizing its bias voltage and O2 flow. After the four-period vertically stacked SiGe/Si Fin structure is introduced, its FinFET device is successfully fabricated under the same fabrication process as the conventional SiGe FinFET. And it attains better drive current Ion, subthreshold slope (SS) and Ion/Ioff ratio electrical performance compared with the conventional SiGe channel FinFET, whose Fin height of SiGe channel is almost equal to total thickness of SiGe in the four-period stacked SiGe/Si channel FinFET. This may be attributed to that the four-period stacked SiGe/Si Fin structure has larger effective channel width (Weff) and may maintain a better quality and surface interfacial performance during the whole fabrication process. Moreover, Si channel of the stacked SiGe/Si channel turning on first also may have contribution to its better electrical properties. This four-period vertically stacked SiGe/Si channel FinFET device has been demonstrated to be a practical candidate for the future technology nodes.

Optimization of triple-junction hydrogenated silicon solar cell nc-Si:H/a-Si:H/a-SiGe:H using step graded Si1‑xGex layer

This paper shows the attempt to increase the performance of triple-junction hydrogenated silicon solar cells with structure nc-Si:H/a-Si:H/a-SiGe:H. The wxAMPS software was used to simulate and optimize the design. In an attempt to increase the performance, an a-SiC:H layer on the p-layer was replaced with an a-Si:H layer and an a-SiGe layer was replaced with a step graded Si1-xGex layer. Then, to achieve the best performing device, we optimized the concentration of germanium and thickness of the step graded Si1-xGex layer. The result shows that the optimum concentration of germanium in the p-i upper layer and i-n lower layer are 0.86 and 0.90, respectively and the optimum thicknesses are 10 nm and 230 nm, respectively. The optimized device performed with an efficiency of 19.08%, adding 3 more percent of efficiency from the original design. Moreover, there is a significant possibility of increasing the efficiency of a triple-junction solar cell by modifying it into a step graded Si1-xGex layer.

Fabrication of Si1-xGex layer on Si substrate by Screen-Printing

The impact of the Al and Ge ratio in the Al-Ge pastes are investigated for fabricating the single crystalline Si1-xGex thick layers on large area Si substrates by screen-printing metallization process. From X-ray reciprocal space maps, Ge fraction in the fabricated Si1-xGex thick layers are found to increase up to 40% with increasing the Ge ratio in the Al-Ge pastes. On the other hand, the interface of the Si and Si1-xGex layers are getting winding with increasing the Ge ratio in the Al-Ge pastes. The Al-Si-Ge phase diagram indicated that uniform SiGe layer can be fabricated by adjusting the Al-Ge ratio in the pastes within the liquid phase region.