Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

FPGA Implementation of Memory Bists using Single Interface

The development of IC integration technologies leads to an extensive use of memories and buffers in different memory intensive applications. Therefore, probability of occurrence of fault in every single read and writes operation is increased in Memory BIST (MBIST). There were many testing approaches that were developed for efficient testing and diagnosis of fault. However, all algorithms are not strengthened enough to detect all possible faults that may be present due to fabrication errors or environmental disturbance. Keeping this in mind and taking the possibility of development of efficient algorithm a hybrid memory testing algorithm is presented. To overcome those drawbacks, pipelining based MBIST designed to detect the all the types of memory faults by utilizing March-C testing algorithm. By introducing the Pipelining approach, majorly path delays are reducing. The proposed architecture designed and verified using Xilinx ISE environment under various testing methods with respect to the different category of memories. The simulation and synthesis results shows that the proposed method shows the enhanced performance with the hardware resource utilization and delay consumption compared to the conventional approaches.

Pseudoexhaustive memory testing based on March A type march tests

The relevance of testing of memory devices of modern computing systems is shown. The methods and algorithms for implementing test procedures based on classical March tests are analyzed. Multiple March tests are highlighted to detect complex pattern-sensitive memory faults. To detect them, the necessary condition that test procedures must satisfy to deal complex faults, is substantiated. This condition is in the formation of a pseudo-exhaustive test for a given number of arbitrary memory cells. We study the effectiveness of single and double application of tests like MATS ++, March C– and March A, and also give its analytical estimates for a different number of k ≤ 10 memory cells participating in a malfunction. The applicability of the mathematical model of the combinatorial problem of the coupon collector for describing multiple memory testing is substantiated. The values of the average, minimum, and maximum multiplicity of multiple tests are presented to provide an exhaustive set of binary combinations for a given number of arbitrary memory cells. The validity of analytical estimates is experimentally shown and the high efficiency of the formation of a pseudo-exhaustive coverage by tests of the March A type is confirmed.

Monitoring, Risk Assessment and Actuation for Alzheimer Patients: A Case Study

Alzheimer is one of the most frequent types of dementia. With the increasing extension of life expectancy, and an increasing incidence above sixty-five years. Near to thirteen million cases are foreseen in 2050 with an estimate cost above two hundred billion dollars in associated care expenses. It becomes important to take measures to ensure quality of life to patients, carers and promote the sustainability of public and personal finances. The major concerns with those patients are memory faults with the tendency for wandering and get lost. The present work proposes a solution for permanent monitoring, risk assessment and reaction, when needed, while extending battery autonomy for the worn device. Data is periodically uploaded to be processed and analysed in a remote infrastructure such as FIWARE. The aim is to establish profiles that better adapt to each citizen of the evergrowing community of dementia patients, including those with Alzheimer disease.