scholarly journals Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 811
Author(s):  
Suleman Alnatheer ◽  
Mohammed Altaf Ahmed
Keyword(s):  
Current System ◽  
Repair Rate ◽  
Optimal Method ◽  
Low Area ◽  
Area Overhead ◽  
Memory Faults ◽  
On Chip ◽  
Almost All ◽  
Embedded Memories ◽  
To Receive

The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

scholarly journals Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
Alireza Monemi ◽  
Chia Yee Ooi ◽  
Muhammad Nadzir Marsono
Keyword(s):  
High Performance ◽  
Clock Cycle ◽  
Network On Chip ◽  
Operating Frequency ◽  
Low Latency ◽  
Core System ◽  
Low Area ◽  
Area Overhead ◽  
Logic Cells ◽  
On Chip

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

HERMES: an infrastructure for low area overhead packet-switching networks on chip

Integration ◽  
2004 ◽  
Vol 38 (1) ◽  
pp. 69-93 ◽  
Author(s):  
Fernando Moraes ◽  
Ney Calazans ◽  
Aline Mello ◽  
Leandro Möller ◽  
Luciano Ost
Keyword(s):  
Packet Switching ◽  
Switching Networks ◽  
Networks On Chip ◽  
Low Area ◽  
Area Overhead ◽  
Packet Switching Networks ◽  
On Chip

scholarly journals NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm

2018 ◽  
Vol 6 (2) ◽  
pp. 105
Author(s):  
A. Kalimuthu ◽  
M. Karthikeyan
Keyword(s):  
Resource Sharing ◽  
Clustering Algorithms ◽  
Font Size ◽  
Core System ◽  
Mesh Structure ◽  
Low Area ◽  
Area Overhead ◽  
Overall Performance ◽  
On Chip ◽  
Many Core

<span style="font-size: 9pt; font-family: 'Times New Roman', serif;">A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique</span>

Reconfigurable Instruction-Set Application-Tuning for DSP

2003 ◽  
Vol 12 (03) ◽  
pp. 333-351 ◽  
Author(s):  
B. Mesman ◽  
Q. Zhao ◽  
N. Busa ◽  
K. Leijten-Nowak
Keyword(s):  
Current System ◽  
High Volume ◽  
Tool Support ◽  
Instruction Set ◽  
Instruction Sets ◽  
Application Characteristics ◽  
On Chip ◽  
Application Tuning ◽  
Primary Contribution ◽  
Hardware Efficiency

In current System-on-Chip (SoC) design, the main engineering trade-off concerns hardware efficiency and design effort. Hardware efficiency traditionally regards cost versus performance (in high-volume electronics), but recently energy consumption emerged as a dominant criterion, even in products without batteries. "The" most effective way to increase HW efficiency is to exploit application characteristics in the HW. The traditional way of looking at HW design tends to consider it a time-consuming and tedious task, however. Given the current lack of HW designers, and the pressure of time-to-market, clearly a desire exists to fine-balance the merits and effort of tuning your HW to your application. This paper discusses methods and tool support for HW application-tuning at different levels of granularity. Furthermore we treat several ways of applying reconfigurable HW to allow both silicon reuse and the ability to tune the HW to the application after fabrication. Our main focus is on a methodology for application-tuning the architecture of DSP datapaths. Our primary contribution is on reusing and generalizing this methodology to application-tuning DSP instruction sets, and providing tool support for efficient compilation for these instruction sets. Furthermore, we propose an architecure for a reconfigurable instruction-decoder, enabling application-tuning of the instruction-set after fabrication.

scholarly journals Securing the wireless emergency alerts system

2021 ◽  
Vol 64 (10) ◽  
pp. 85-93
Author(s):  
Jihoon Lee ◽  
Gyuhong Lee ◽  
Jinsung Lee ◽  
Youngbin Im ◽  
Max Hollingsworth ◽  
...  
Keyword(s):  
Open Source ◽  
Open Source Software ◽  
Software Defined Radio ◽  
Severe Weather ◽  
Base Stations ◽  
The Public ◽  
Software Libraries ◽  
Amber Alerts ◽  
Almost All ◽  
To Receive

Modern cell phones are required to receive and display alerts via the Wireless Emergency Alert (WEA) program, under the mandate of the Warning, Alert, and Response Act of 2006. These alerts include AMBER alerts, severe weather alerts, and (unblockable) Presidential Alerts, intended to inform the public of imminent threats. Recently, a test Presidential Alert was sent to all capable phones in the U.S., prompting concerns about how the underlying WEA protocol could be misused or attacked. In this paper, we investigate the details of this system and develop and demonstrate the first practical spoofing attack on Presidential Alerts, using commercially available hardware and modified open source software. Our attack can be performed using a commercially available software-defined radio, and our modifications to the open source software libraries. We find that with only four malicious portable base stations of a single Watt of transmit power each, almost all of a 50,000-seat stadium can be attacked with a 90% success rate. The real impact of such an attack would, of course, depend on the density of cellphones in range; fake alerts in crowded cities or stadiums could potentially result in cascades of panic. Fixing this problem will require a large collaborative effort between carriers, government stakeholders, and cellphone manufacturers. To seed this effort, we also propose three mitigation solutions to address this threat.

scholarly journals E-Governance in India to Combat COVID-19

2021 ◽  
Vol 8 (12) ◽  
pp. 1-5
Author(s):  
Dr. Mangesh M. Ghonge ◽  
Mr. Deepak Pathratkar
Keyword(s):  
Private Sector ◽  
Mutual Contact ◽  
Work From Home ◽  
The World ◽  
Current Scenario ◽  
The Government ◽  
Almost All ◽  
To Receive

Viral pandemics are a serious threat. COVID-19 is not the first, and it won't be the last. As the whole world is going through the black phase of COVID-19 virus, the scientists are trying to invent a fighting vaccine against the same. Each and every sector in every part of the world is infected by the outburst of the fatal virus. Right from business and trade to sports and entertainment, every aspect of life is suffering a lot. To combat the outbreak of the pandemic, most of the countries have used partial to complete lockdown as the only weapon to stop the spread of the virus. In the current scenario, almost all the private sector companies as well as the government offices have suggested all the employees to work from home to stop the community spread of the disease that may occur if people come in mutual contact. While we think of governing authorities around the world, each and every government provides some e-facilities to their citizens to some what extent. Generally E-Governance can be stated as the facility to receive each and everything electronically i.e. you don’t need to go to outside home to receive any document or order. In this paper, we briefly described the different aspects of e-governance.

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