Hardware Update through Digital TV Signals

This paper presents a new hardware reconfiguration approach named hardware reconfiguration through digital television (HARD), which can update FPGA hardware modules based on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams) signaled and broadcast through open DTV signals via data streaming to be identified, acquired, decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers. Service information content, specially designed for identifying and describing the characteristics of multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary information in the traditional DTV style. The receiver framework, in turn, checked whether those characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments performed with an implementation of the proposed methodology confirmed its feasibility and showed that remounting and reconfiguration times were satisfactory and presented no blocking aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices, minimize device costs in the long term, and provide better hardware reuse.

Fault Analysis and Non-Redundant Fault Tolerance in 3-Level Double Conversion UPS Systems Using Finite-Control-Set Model Predictive Control

Fault-tolerance is critical in power electronics, especially in Uninterruptible Power Supplies, given their role in protecting critical loads. Hence, it is crucial to develop fault-tolerant techniques to improve the resilience of these systems. This paper proposes a non-redundant fault-tolerant double conversion uninterruptible power supply based on 3-level converters. The proposed solution can correct open-circuit faults in all semiconductors (IGBTs and diodes) of all converters of the system (including the DC-DC converter), ensuring full-rated post-fault operation. This technique leverages the versatility of Finite-Control-Set Model Predictive Control to implement highly specific fault correction. This type of control enables a conditional exclusion of the switching states affected by each fault, allowing the converter to avoid these states when the fault compromises their output but still use them in all other conditions. Three main types of corrective actions are used: predictive controller adaptations, hardware reconfiguration, and DC bus voltage adjustment. However, highly differentiated corrective actions are taken depending on the fault type and location, maximizing post-fault performance in each case. Faults can be corrected simultaneously in all converters, as well as some combinations of multiple faults in the same converter. Experimental results are presented demonstrating the performance of the proposed solution.

Secure Boot for Reconfigurable Architectures

Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements a secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.

Secure Boot for Reconfigurable Architectures

Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.