Automated and adaptive geometry preparation for ar/vr-applications

Product visualization in AR/VR applications requires a largely manual process of data preparation. Previous publications focus on error-free triangulation or transformation of product structure data and display attributes for AR/VR applications. This paper focuses on the preparation of the required geometry data. In this context, a significant reduction in effort can be achieved through automation. The steps of geometry preparation are identified and examined concerning their automation potential. In addition, possible couplings of sub-steps are discussed. Based on these explanations, a structure for the geometry preparation process is proposed. With this structured preparation process, it becomes possible to consider the available computing power of the target platform during the geometry preparation. The number of objects to be rendered, the tessellation quality, and the level of detail can be controlled by the automated choice of transformation parameters. Through this approach, tedious preparation tasks and iterative performance optimization can be avoided in the future, which also simplifies the integration of AR/VR applications into product development and use. A software tool is presented in which partial steps of the automatic preparation are already implemented. After an analysis of the product structure of a CAD file, the transformation is executed for each component. Functions implemented so far allow, for example, the selection of assemblies and parts based on filter options, the transformation of geometries in batch mode, the removal of certain details, and the creation of UV maps. Flexibility, transformation quality, and timesavings are described and discussed.

Architecting an Advanced Maturity Model for Business Processes in the Gig Economy: A Platform-Based Project Standardization

The business continuity of the gig economy is strongly driven by the operator’s ability to manage the maturity of business processes. Moreover, projects in the gig economy are risky due to the lack of monitoring and involvement of actors’ profiles. When business processes become mature as the target, platform-based project results can satisfy actors’ expectations. To reach targeted maturity, operators need to standardize their business processes. This standardization is actualized in a maturity model as a benchmark and guideline tool. It exposes how mature the current business processes are and the required improvements. This research aims to construct a maturity model systematically and comprehensively to encourage operators in the gig economy (as the model user) to improve the products and services delivered. This research has constructed a new maturity model for business processes using the maturity model development phases initiated by de Bruin et al. It explores the gig economy ecosystem in Indonesia. This research initiates the maturity model by collecting 48 factors in the gig economy. It continues by composing 13 determinant candidates as representations of the factors. After an empirical test involving 200 people (consisting of gig worker, client, and operator) and two iterations of mixed-method validation involving 16 experts, this research generates ten determinants classified into three dimensions: actors, platforms, and transactions. The maturity level of each determinant is measured to indicate its position toward digital business continuity.

spaceAPPS – A modular approach for on-board software

Software modularity and partial qualification capabilities are key enablers to produce cost efficient software in highly regulated domains. The modular concept (called spaceAPPS) described in this paper has been developed in the frame of the OPS-SAT project aiming at missions where flexibility is one of the success factors. spaceAPPS implements a novel software architecture for satellites inspired by the Apps concept of modern smartphones. In the European space domain the operation of a satellite is based on a set of 18 services. Accordingly, in spaceApps these services are mapped to individual Apps. This is not a one-to-one mapping which means that one App implements one or more services. During OPS-SAT ground testing it was demonstrated that functionality could be easily added through a new App or updated through replacing an existing App. Also during OPS-SAT ground testing it could be shown that a failing UserApp did not impact the basic apps to operate the satellite. Thus, it is possible to run applications of different criticality on the same platform. With operating systems supporting time and space separation the risk of failure propagation can be further reduced. The implementation of a partial validation approach, i. e. testing of third-party Apps in a representative environment and not running the validation on the target platform is feasible but was not demonstrated.

Automated and Adaptive Geometry Preparation for AR/VR-Applications

Product visualization in AR/VR applications requires a largely manual process of data preparation. Previous publications focus on error-free triangulation or transformation of product structure data and display attributes for AR/VR applications. This paper focuses on the preparation of the required geometry data. In this context, a significant reduction in effort can be achieved through automation. The steps of geometry preparation are identified and examined with respect to their automation potential. In addition, possible couplings of sub-steps are discussed. Based on these explanations, a structure for the geometry preparation process is proposed. With this structured preparation process it becomes possible to consider the available computing power of the target platform during the geometry preparation. The number of objects to be rendered, the tessellation quality and the level of detail can be controlled by the automated choice of transformation parameters. We present a software tool in which partial steps of the automatic preparation are already implemented. After an analysis of the product structure of a CAD file, the transformation is executed for each component. Functions implemented so far allow, for example, the selection of assemblies and parts based on filter options, the transformation of geometries in batch mode, the removal of certain details and the creation of UV maps. Flexibility, transformation quality and time savings are described and discussed.

Classic McEliece on the ARM Cortex-M4

This paper presents a constant-time implementation of Classic McEliece for ARM Cortex-M4. Specifically, our target platform is stm32f4-Discovery, a development board on which the amount of SRAM is not even large enough to hold the public key of the smallest parameter sets of Classic McEliece. Fortunately, the flash memory is large enough, so we use it to store the public key. For the level-1 parameter sets mceliece348864 and mceliece348864f, our implementation takes 582 199 cycles for encapsulation and 2 706 681 cycles for decapsulation. Compared to the level-1 parameter set of FrodoKEM, our encapsulation time is more than 80 times faster, and our decapsulation time is more than 17 times faster. For the level-3 parameter sets mceliece460896 and mceliece460896f, our implementation takes 1 081 335 cycles for encapsulation and 6 535 186 cycles for decapsulation. In addition, our implementation is also able to carry out key generation for the level-1 parameter sets and decapsulation for level-5 parameter sets on the board.

Time Measurement and Control Blocks for Bare-Metal C++ Applications

Precisely timed execution of resource constrained bare-metal applications is difficult, because the embedded software developer usually has to implement and check the timeliness of the executed application through manual interaction with timers or counters. In the scope of this work, we propose a combined timing specification and concept for time annotation and control blocks in C++. Our proposed blocks can be used to measure and profile software block execution time. Furthermore, it can be used to control and enforce the software time behavior at runtime. After the application of these time blocks, a trace-based verification against the block-based timing specification can be performed to obtain evidence on the correct implementation and usage of the time blocks on the target platform. We have implemented our time block concept in a C++ library and tested it on an ARM Cortex A9 bare-metal platform. The combined usage of timing specification and our time block library has been successfully evaluated on a critical flight-control software for a multi-rotor system.

Practical Examples of Automated Development of Efficient Parallel Programs

In this chapter, some examples of application of the developed software tools for design, generation, transformation, and optimization of programs for multicore processors and graphics processing units are considered. In particular, the algebra-algorithmic-integrated toolkit for design and synthesis of programs (IDS) and the rewriting rules system TermWare.NET are applied for design and parallelization of programs for multicore central processing units. The developed algebra-dynamic models and the rewriting rules toolkit are used for parallelization and optimization of programs for NVIDIA GPUs supporting the CUDA technology. The TuningGenie framework is applied for parallel program auto-tuning: optimization of sorting, Brownian motion simulation, and meteorological forecasting programs to a target platform. The parallelization of Fortran programs using the rewriting rules technique on sample problems in the field of quantum chemistry is examined.

Secure Boot for Reconfigurable Architectures

Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements a secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.

Secure Boot for Reconfigurable Architectures

Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.