ZRO Drift Reduction of MEMS Gyroscopes via Internal and Packaging Stress Release

Zero-rate output (ZRO) drift induces deteriorated micro-electromechanical system (MEMS) gyroscope performances, severely limiting its practical applications. Hence, it is vital to explore an effective method toward ZRO drift reduction. In this work, we conduct an elaborate investigation on the impacts of the internal and packaging stresses on the ZRO drift at the thermal start-up stage and propose a temperature-induced stress release method to reduce the duration and magnitude of ZRO drift. Self-developed high-Q dual-mass tuning fork gyroscopes (TFGs) are adopted to study the correlations between temperature, frequency, and ZRO drift. Furthermore, a rigorous finite element simulation model is built based on the actual device and packaging structure, revealing the temperature and stresses distribution inside TFGs. Meanwhile, the relationship between temperature and stresses are deeply explored. Moreover, we introduce a temperature-induced stress release process to generate thermal stresses and reduce the temperature-related device sensitivity. By this way, the ZRO drift duration is drastically reduced from ~2000 s to ~890 s, and the drift magnitude decreases from ~0.4 °/s to ~0.23 °/s. The optimized device achieves a small bias instability (BI) of 7.903 °/h and a low angle random walk (ARW) of 0.792 °/√ h, and its long-term bias performance is significantly improved.

ZRO Drift Reduction of MEMS Gyroscopes via Internal and Packaging Stress Release

Zero-rate output (ZRO) drift induces deteriorated micro-electromechanical system (MEMS) gy-roscope performances, severely limiting its practical applications. Hence, it is vital to explore an effective method toward ZRO drift reduction. In this work, we conduct an elaborate investigation on the impacts of the internal and packaging stresses on the ZRO drift at the thermal start-up stage, and propose a temperature-induced stress release method to reduce the duration and magnitude of ZRO drift. Self-developed high-Q dual mass tuning fork gyroscopes (TFGs) are adopted to study the correlations between temperature, frequency and ZRO drift. Furthermore, a rigorous finite element simulation model is built based on the actual device and packaging structure, revealing the temperature and stresses distribution inside TFGs. Meanwhile, the relationship between temperature and stresses are deeply explored. Moreover, we introduce a temperature-induced stress release process to generate thermal stresses and reduce the temperature-related device sensitivity. By this way, the ZRO drift duration is drastically reduced from ~2000 s to ~890 s, and the drift magnitude decreases from ~0.4 °/s to ~0.23 °/s. This stress release method achieves a small bias instability (BI) of 7.903 °/h and a low angle random walk (ARW) of 0.792 °/√h, and the long-term bias performance is significantly improved.

On the Correlation Between Residual Stresses and Displacements of the Polycrystalline Lattice: an Experimental Strategy

This work aims to propose a micro-indent method to evaluate the correlation between the relaxation of residual stresses and the shape changes of the polycrystalline lattice in specimens of a rolled plate of AA 6082-T6 aluminium alloy. Rolling strengthens the surface of the plate by introducing compressive residual stresses. Then, these stresses are relaxed by thermal distension. The method of micro-indents allowed measuring residual displacements with an error below ± 300 nm. The results obtained reveal that the rolling direction plays a vital role in terms of asymmetric expansion of the lattice. Furthermore, the lattice accumulates and restores elastic strain energy in the clockwise and anti-clockwise direction of rotation, alternatively. Finally, when the stress release process is finishing, the lattice adjusts the angle of rotation to approximate to the initial geometric shape.

Autocorrelations in pulsar glitch waiting times and sizes

ABSTRACT Among the five pulsars with the most recorded rotational glitches, only PSR J0534+2200 is found to have an autocorrelation between consecutive glitch sizes that differs significantly from zero (Spearman correlation coefficient ρ = −0.46, p-value = 0.046). No statistically compelling autocorrelations between consecutive waiting times are found. The autocorrelation observations are interpreted within the framework of a predictive meta-model describing stress release in terms of a state-dependent Poisson process. Specific combinations of size and waiting time autocorrelations are identified, alongside combinations of cross-correlations and size and waiting time distributions, that are allowed or excluded within the meta-model. For example, future observations of any ‘quasi-periodic’ glitching pulsar, such as PSR J0537–6910, should not reveal a positive waiting time autocorrelation. The implications for microphysical models of the stress-release process driving pulsar glitches are discussed briefly.

DEVELOPMENT OF AN ULTRA THIN DIE-TO-WAFER FLIP CHIP STACKING PROCESS FOR 2.5D INTEGRATION

3D integration relying on novel vertical interconnection technologies opens the gate to powerful microelectronic systems in ultra-thin packages answering the demand of the mobile market. Among these, die-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by, in one hand, the increase of the die surface and the number of I/Os and, on the other hand, the reduction of the vertical dimensions. In our integration scheme we have achieved flip chip stacking (or Face to Face) of 35 μm ultra-thin dies with low stand-off (< 15 μm) copper micro-bumps and tin-silver-copper solders (SAC). Ultra-thin dies are prepared using dicing before grinding (DBG) technique. After DBG, plasma stress release process is applied to the backside of the singulated chips. Copper μbump technology is challenging with this very low profile stacking since the current flip chip process is no longer adapted to this geometry and that the die flatness tolerance become very critical to obtain a high soldering yield. Process improvements have been achieved on the copper pillar fabrication itself with several metallurgy stack configurations as well as new processes using damascene techniques. Furthermore, innovative technologies have been deployed on the pick and place and collective soldering processes. Intermetallic formation during reflow process is achieved through transient liquid phase (TLP) reaction leading to thorough consumption of the tin layer and to the formation of Cu6Sn5 and Cu3Sn compounds. Capillary underfill is finally successfully applied in the narrow die-to-wafer gap by jetting technique. After optimization, electrical tests show a very high yield close to 100% over a representative number of fully populated wafers. Reliability tests have also been carried out at wafer level exhibiting no significant resistance increase or yield loss over 1000 thermal cycles between −40 and +125°C.