scholarly journals Efficient Designs of Quantum Adder/Subtractor Using Universal Reversible Gate on IBM Q

Symmetry ◽  
2021 ◽  
Vol 13 (10) ◽  
pp. 1842
Author(s):  
Mohamed Osman ◽  
Khaled El-Wazan
Keyword(s):  
Quantum Computing ◽  
Symmetric Group ◽  
Success Probability ◽  
Quantum Cost ◽  
Logical Operations ◽  
Gate Count ◽  
Reversible Gate ◽  
Addition And Subtraction ◽  
Logic Unit ◽  
Ibm Quantum Experience

Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.

Efficient designs of reversible BCD to EX-3 Converter with low quantum cost in nanoscale

2020 ◽  
Vol 18 (05) ◽  
pp. 2050020 ◽  
Author(s):  
Mojtaba Noorallahzadeh ◽  
Mohammad Mosleh
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Computing Systems ◽  
Gate Count ◽  
Reversible Gate ◽  
Significant Research ◽  
Research Domain ◽  
Better Than

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh[Formula: see text]Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA

2017 ◽  
Vol 26 (09) ◽  
pp. 1750145 ◽  
Author(s):  
Neeraj Kumar Misra ◽  
Bibhash Sen ◽  
Subodh Wairya ◽  
Bandan Bhoi
Keyword(s):  
Circuit Design ◽  
Low Cost ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Gate ◽  
Majority Voter ◽  
Decoder Design ◽  
Decoder Circuit

In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the [Formula: see text]-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground on QCADesigner achieved 0.63 μm2 area, 15 majority voter gates, and 451 cell complexities. It is observed that nanoelectronics has also made an inevitable contribution in the area of QCA.

Efficient reversible quantum design of sig-magnitude to two's complement converters

2020 ◽  
Vol 20 (9&10) ◽  
pp. 747-765
Author(s):  
F. Orts ◽  
G. Ortega ◽  
E.M. E.M. Garzon
Keyword(s):  
Quantum Computing ◽  
Scientific Community ◽  
Quantum Computer ◽  
Fault Tolerant ◽  
State Of The Art ◽  
The Other ◽  
Quantum Computers ◽  
Binary Number ◽  
Quantum Cost ◽  
The One

Despite the great interest that the scientific community has in quantum computing, the scarcity and high cost of resources prevent to advance in this field. Specifically, qubits are very expensive to build, causing the few available quantum computers are tremendously limited in their number of qubits and delaying their progress. This work presents new reversible circuits that optimize the necessary resources for the conversion of a sign binary number into two's complement of N digits. The benefits of our work are two: on the one hand, the proposed two's complement converters are fault tolerant circuits and also are more efficient in terms of resources (essentially, quantum cost, number of qubits, and T-count) than the described in the literature. On the other hand, valuable information about available converters and, what is more, quantum adders, is summarized in tables for interested researchers. The converters have been measured using robust metrics and have been compared with the state-of-the-art circuits. The code to build them in a real quantum computer is given.

scholarly journals A quantum Hopfield associative memory implemented on an actual quantum processor

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Nathan Eli Miller ◽  
Saibal Mukhopadhyay
Keyword(s):  
Machine Learning ◽  
Quantum Computing ◽  
Associative Memory ◽  
Leading Edge ◽  
Memory Capacity ◽  
Quantum Processor ◽  
Significant Step ◽  
Machine Learning Applications ◽  
Noise Models ◽  
Ibm Quantum Experience

AbstractIn this work, we present a Quantum Hopfield Associative Memory (QHAM) and demonstrate its capabilities in simulation and hardware using IBM Quantum Experience.. The QHAM is based on a quantum neuron design which can be utilized for many different machine learning applications and can be implemented on real quantum hardware without requiring mid-circuit measurement or reset operations. We analyze the accuracy of the neuron and the full QHAM considering hardware errors via simulation with hardware noise models as well as with implementation on the 15-qubit ibmq_16_melbourne device. The quantum neuron and the QHAM are shown to be resilient to noise and require low qubit overhead and gate complexity. We benchmark the QHAM by testing its effective memory capacity and demonstrate its capabilities in the NISQ-era of quantum hardware. This demonstration of the first functional QHAM to be implemented in NISQ-era quantum hardware is a significant step in machine learning at the leading edge of quantum computing.

scholarly journals A shared-cube approach to ESOP-based synthesis of reversible logic

2011 ◽  
Vol 24 (3) ◽  
pp. 385-402 ◽  
Author(s):  
Noor Nayeem ◽  
Jacqueline Rice
Keyword(s):  
Power Loss ◽  
Heat Dissipation ◽  
Logic Synthesis ◽  
Reversible Logic ◽  
Experimental Results ◽  
Quantum Cost ◽  
Toffoli Gate ◽  
Gate Count ◽  
Computing Industry ◽  
Synthesis Approach

Reversible logic is being suggested as a possibility for overcoming potential power loss and heat dissipation problems that the computing industry may soon be at a loss to overcome. However, for reversible logic to be a solution we must have techniques for synthesizing function descriptions to reversible circuits. This paper presents an improved ESOP-based reversible logic synthesis approach which leverages situations where cubes are shared by multiple outputs and ensures that the implementation of each cube requires just one Toffoli gate. It has the potential to minimize both gate count and quantum cost, and in fact our experimental results show that this technique can reduce the quantum cost up to 75% compared to results from the existing work.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

A new design of a low-power reversible Vedic multiplier

2020 ◽  
Vol 18 (03) ◽  
pp. 2050002
Author(s):  
Meysam Rashno ◽  
Majid Haghparast ◽  
Mohammad Mosleh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Reversible Logic ◽  
Arithmetic Circuits ◽  
Quantum Cost ◽  
Computing Systems ◽  
Vedic Multiplier ◽  
Wide Range ◽  
Logic Unit

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

scholarly journals Experimental test of non-macrorealistic cat states in the cloud

2020 ◽  
Vol 6 (1) ◽  
Author(s):  
Huan-Yu Ku ◽  
Neill Lambert ◽  
Feng-Jui Chan ◽  
Clive Emary ◽  
Yueh-Nan Chen ◽  
...  
Keyword(s):  
Quantum Computing ◽  
Quantum Theory ◽  
Experimental Test ◽  
Classical World ◽  
Potential Measure ◽  
Cat States ◽  
Ibm Quantum Experience ◽  
Invasive Measurement

AbstractThe Leggett–Garg inequality attempts to classify experimental outcomes as arising from one of two possible classes of physical theories: those described by macrorealism (which obey our intuition about how the macroscopic classical world behaves) and those that are not (e.g., quantum theory). The development of cloud-based quantum computing devices enables us to explore the limits of macrorealism. In particular, here we take advantage of the properties of the programmable nature of the IBM quantum experience to observe the violation of the Leggett–Garg inequality (in the form of a ‘quantum witness’) as a function of the number of constituent systems (qubits), while simultaneously maximizing the ‘disconnectivity’, a potential measure of macroscopicity, between constituents. Our results show that two- and four-qubit ‘cat states’ (which have large disconnectivity) are seen to violate the inequality, and hence can be classified as non-macrorealistic. In contrast, a six-qubit cat state does not violate the ‘quantum witness’ beyond a so-called clumsy invasive-measurement bound, and thus is compatible with ‘clumsy macrorealism’. As a comparison, we also consider un-entangled product states with n = 2, 3, 4 and 6 qubits, in which the disconnectivity is low.

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