scholarly journals The MU5 Instruction Pipeline

1972 ◽  
Vol 15 (1) ◽  
pp. 42-50 ◽  
Author(s):  
R. N. Ibbett
Keyword(s):  
Instruction Pipeline

Evaluation of SEE on a 32-bit Microprocessor by Laser Test and Heavy Ion Test

2015 ◽  
Vol 1105 ◽  
pp. 391-396
Author(s):  
Chun Qing Yu ◽  
Long Fan ◽  
Suge Yue ◽  
Jian Hua Ma ◽  
Hong Chao Zheng
Keyword(s):  
Laser Pulse ◽  
Low Cost ◽  
Step Length ◽  
Heavy Ion ◽  
Spot Size ◽  
Single Event ◽  
Laser Spot Size ◽  
Scanning Step ◽  
Instruction Pipeline ◽  
Made In

In this paper the SEE (single event effects) of different parts of device were explored on a 32-bit microprocessor with a five-stage instruction pipeline by laser test and heavy ion test. The cross section curves for different function units were obtained and the comparison of the dates obtained from laser test and heavy ion tests was made. In addition, laser test under different scanning steps were made which indicate that when the scanning step length is in small steps which is considerably equivalent to the laser spot size, there is little change in the number of single event errors caused by each laser pulse. Wherever with the scanning step increasing, the number of single event errors caused by each laser pulse will be reduced. Experiment results suggest that there are differences between laser test and the heavy ion test but have a similar trend. The pulsed laser is an extremely powerful and low-cost technique for SEE testing and will provide invaluable information in characterizing SEE in integrate circuits.

The Secondary Instruction Pipeline

1979 ◽  
pp. 84-107
Author(s):  
Derrick Morris ◽  
Roland N. Ibbett
Keyword(s):  
Secondary Instruction ◽  
Instruction Pipeline

scholarly journals A CUDA-QUDA architecture, Hyperscale-Data Quantum GPUs

2019 ◽  
Author(s):  
Anil Kumar Bheemaiah
Keyword(s):  
Operating System ◽  
Spin Waves ◽  
Stream Processing ◽  
Array Architecture ◽  
System P ◽  
Gpu Architectures ◽  
Instruction Pipeline ◽  
Processing Architecture ◽  
Better Than

Abstract:QUDA is an architecture similar to CUDA for HPC applications of Quantum GPU architectures to be used in conjunction with GPU and MCU based processing. There is no QUDA pipeline similar to a stream processing architecture or an out of order instruction pipeline. True ILP is achieved with a QUDA architecture, which is better than quasi-parallelism in a CUDA or scalar/vector architecture.Keywords: QUDA architecture, HPC, Quantum Cloud, Qiskit, spin waves, spintronic, hyper-data, quantum operating system.What:Quantum Unified Compute Architecture or QUDA architectures is the use of Q and Qiskit for a reconfigurable quantum array architecture on spintronic units with a reconfigurable scheduler for a quantum operating system.

IMPLEMENTATION OF THE BRANCH PREDICTION SCHEMES FOR THE MICROPROCESSOR OF RISC-V ARCHITECTURE

2018 ◽  
pp. 49-55
Author(s):  
E. M. Abramov
Keyword(s):  
Prediction Accuracy ◽  
Branch Prediction ◽  
Limiting Factors ◽  
Prediction Methods ◽  
Hardware Cost ◽  
Control Transfer ◽  
Prediction Module ◽  
Pipeline Processing ◽  
Instruction Pipeline

One of the limiting factors for increasing the performance of CPU computation pipeline is the pipelining of control transfer instructions. This article provides a review of the problems of raising the instruction pipeline efficiency while executing the branch instructions, by the example of microarchitecture with the implementation of open RISC-V ISA. It gives a description of the various methods of resolving the control hazards. Implementations of the various static and dynamic branch prediction methods, as well as the scheme of calculating a jump address, has been provided. For the dynamic schemes this article gives an estimate of the dependency of prediction accuracy from the size of the branch history tables. Also, it contains the results of synthesis, which allow to estimate the hardware cost of the implementation of given schemes. It has been discovered that the presence of dynamic branch prediction module at the computation pipeline is helping to raise the efficiency of pipeline processing.

scholarly journals Improvement of Standard and Non-Standard Floating-Point Operators

1970 ◽  
Vol 6 (1) ◽  
pp. 19-32
Author(s):  
Pongyupinpanich Surapong ◽  
Francois Philipp ◽  
Faizal Arya Samman ◽  
Manfred Glesner
Keyword(s):  
Clock Cycle ◽  
General Purpose ◽  
Floating Point ◽  
Instruction Set ◽  
General Purpose Processor ◽  
Ieee Standard ◽  
Xilinx Fpga ◽  
Instruction Pipeline ◽  
Point Arithmetic ◽  
Standard Operations

This paper presents the design and analysis of a floating-point arithmetic accelerator in compliance with the IEEE standard single precision floatingpoint format. The accelerator can be used to extend a general-purpose processor such as Motorola MC6820, where floating-point execution units are unembedded by default. It implements standard and non-standard mathematic functions, addition/subtraction, multiplication, Product-of-Sum and Sumof- Product through a micro-instruction set supported by both single and multi-processors systems. The architecture of the unit is based on an instruction pipeline which can simultaneously fetch and execute an instruction within one clock cycle. The non-standard operations such as Product-of-Sum and Sum-of-Product are introduced to compute threeinput operands. The algorithm complexity and hardware critical delay are determined for each operator. The synthesis results of the accelerator on a Xilinx FPGA Virtex 5 xc5vlx110t-3ff-1136 and on Faraday 130-nm Silicon technology report that the design respectively achieves 200 MHz and 1 GHz.

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