Using a Dielectric Capacitance Cell to Determine the Dielectric Properties of Pure Sand Artificially Contaminated with Pb, Cd, Fe, and Zn

This paper presents a new method of dielectric capacitance cell as a proposed device for measuring the impedance of pure sand artificially contaminated with four heavy metals. Dielectric constant and loss factor of clean and contaminated sand at various levels were calculated from the measured sand impedances. The advantages and benefits of using the proposed dielectric capacitance cell were its low cost, simple calculation, calibration procedures, portable and lightweight, and easy to modify the electrodes to suit testing in the field. Pure sand was saturated with water artificially polluted in the lab with Pb, Cd, Fe, and Zn at heavy metal contents 0, 7.5, 15, 22.5, and 30 mg/kg of sand. The dielectric properties of polluted sand were evaluated at a frequency range from 100 kHz to 1000 kHz. The polluted sand exhibit different dielectric constants and loss factors from the unpolluted sand. The results also indicate that the dielectric constant decreases with increasing pollution level for all heavy metals. This may attribute to the polarization mechanism change with existing heavy metal. The loss factor of sand increases with the increasing pollution level. This may be explained by the increase of ionic conductivity of pore water with heavy metal in the sand. Sand polluted with heavy metal with higher resistivity and density possess a higher dielectric constant and lower loss factor than other polluted metals. Evaluation of the dielectric characteristics of polluted sand could have the potential to monitor heavy metal pollution. Even with promising results obtained with the proposed dielectric device, it is necessary to explore several other factors affecting the measurements such as sand water content, soil texture, and type of soil. Also, testing polluted soil near industrial pollution is needed.

Failure Analysis Induced by Memory Cell Plate Noise in High-Density DRAMs

As the DRAM structure is miniaturized, the cell capacitance is reduced and resistance is increased. Because of this change, the DRAM operation is more sensitive than previous generations to changes of the device elements. The device elements consist of cell capacitance, Bit Line (BL) capacitance, cell node resistance, supply-voltage and the surround noise. The elements were changed by decreasing the cell node dimensions. The write time (tWR) is degraded by changing the elements. In particular, the noise is very variable element on change of surrounding cell phase which is data1 or data 0. In this paper, we show that one of the most dominant contributors to failure is the plate noise and explain how plate voltage level affects tWR delay. The effect of the plate voltage modulation can be correlated with ∆Vbl which is bit line level difference to read out the data. We define this phenomenon as the plate dc noise effect and propose a model in miniaturized DRAM.

Nanocluster NVM Cells Metrology: Window Formation, Relaxation and Charge Retention Measurements

In the paper a measurement technique for study main technical and physical parameters of nanocluster non-volatile memory capacitance cell is presented. The charging/discharging process features associated with nanoclusters (nanocrystals) incorporated into gate dielectric are discussed. Original equipment for fast capacitance measurements based on computer interfaces is considers.