MEASUREMENT OF WIND POWER AND ENERGY USING AN ANEMOMETER WITHOUT MOVING PARTS

The paper deals with the application of a newly developed anemometer without moving parts. It is digitized and has built-in electronics that convert the vibrations of two aluminum fixed frames into two digital signals: one, which shows the strength (speed absolute value)) of the wind, and the other, which shows its direction. Both of these signals are used to calculate wind power and energy. Earlier works have shown that the two-bit stochastic digital measurement method overcomes (eliminates) the problem of the offset of the analog adder. The authors of this paper apply this idea to the digital output of the sensor, where the role of the offset of the analog adder is taken over by the integral nonlinearity of the digital output of the anemometer. The first step in this direction is digitally dithering the sensor output. This principle is presented in detail, as well as a rough estimate of the accuracy gain in measuring wind energy. The obtained result shows that the accuracy in measuring wind energy is not worse than the limit accuracy in the case of a cup anemometer that generates sinusoidal voltage.

RRAM-based CAM combined with time-domain circuits for hyperdimensional computing

Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM (RRAM)-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered. The proposed design uses 65 nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2, consumes 13.6 pJ of energy per 1 k query within 10 ns clock cycle. It shows a reduction of ~ 31 × in area and ~ 3 × in energy consumption compared to fully digital ASIC implementation using 65 nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered.The proposed design uses 65nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2 , consumes 13.6 pJ of energy per 1k query within 10 ns clock cycle for 10 classes. It shows a reduction of ∼ 31× in area and ∼ 3× in energy consumption compared to fully digital ASIC implementation using 65nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

Metabolic Perceptrons for Neural Computing in Biological Systems

Synthetic biological circuits are promising tools for developing sophisticated systems for medical, industrial, and environmental applications. So far, circuit implementations commonly rely on gene expression regulation for information processing using digital logic. Here, we present a new approach for biological computation through metabolic circuits designed by computer-aided tools, implemented in both whole-cell and cell-free systems. We first combine metabolic transducers to build an analog adder, a device that sums up the concentrations of multiple input metabolites. Next, we build a weighted adder where the contributions of the different metabolites to the sum can be adjusted. Using a computational model trained on experimental data, we finally implement two four-input “perceptrons” for desired binary classification of metabolite combinations by applying model-predicted weights to the metabolic perceptron. The perceptron-mediated neural computing introduced here lays the groundwork for more advanced metabolic circuits for rapid and scalable multiplex sensing.

Data-rate-efficient CMOS modulator for wireless biomedical sensor network applications

A 0.18 µm CMOS Binary Frequency Shift Keying Modulator with a novel frequency synthesizer structure is proposed in this paper. Based on an analog adder technique being the backbone of the synthesizer, this prototype demonstrates a compact modulator with low complexity, which achieves 1 Mbps at 400 MHz while dissipating 3.1 mW at 1.5 V supply. The proposed design is ideal for biomedical sensor network systems including distributed wearable body area network.