2010 Symposium on VLSI Technology
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96
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18
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Published By IEEE

9781424454518
Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Short-channel performance and mobility analysis of <110>- and <100>-oriented tri-gate nanowire MOSFETs with raised source/drain extensions

2010 ◽  
Author(s):  
M. Saitoh ◽  
Y. Nakabayashi ◽  
H. Itokawa ◽  
M. Murano ◽  
I. Mizushima ◽  
...  
Keyword(s):  
Mobility Analysis ◽  
Short Channel ◽  
Nanowire Mosfets ◽  
Channel Performance

GaN-on-Si: A scalable material system to realize cost effective next-generation solid state lighting and power devices

2010 ◽  
Author(s):  
S. Decoutere ◽  
H. Osman ◽  
J. Dekoster ◽  
B. Dutta ◽  
S. Biesemans
Keyword(s):  
Solid State ◽  
Cost Effective ◽  
Solid State Lighting ◽  
Material System ◽  
Next Generation ◽  
Power Devices ◽  
Gan On Si

Acknowledgement

2010 ◽  
Author(s):  
Susumu Kohyama

Ion-implantation-based low-cost Hk/MG process for CMOS low-power application

2010 ◽  
Author(s):  
C. Ortolland ◽  
S. Sahhaf ◽  
V. Srividya ◽  
R. Degraeve ◽  
K. Saino ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Low Power ◽  
Low Cost ◽  
Power Application

Si tunnel transistors with a novel silicided source and 46mV/dec swing

2010 ◽  
Author(s):  
Kanghoon Jeon ◽  
Wei-Yip Loh ◽  
Pratik Patel ◽  
Chang Yong Kang ◽  
Jungwoo Oh ◽  
...  
Keyword(s):  
Tunnel Transistors

SiC technologies for future energy electronics

2010 ◽  
Author(s):  
Tsunenobu Kimoto

Statistical evaluation for trap energy level of RTS characteristics

2010 ◽  
Author(s):  
A. Teramoto ◽  
T. Fujisawa ◽  
K. Abe ◽  
S. Sugawa ◽  
T. Ohmi
Keyword(s):  
Energy Level ◽  
Statistical Evaluation ◽  
Trap Energy

Foreword

2010 ◽  

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

2010 ◽  
Author(s):  
V. S. Basker ◽  
T. Standaert ◽  
H. Kawasaki ◽  
C.-C. Yeh ◽  
K. Maitra ◽  
...  
Keyword(s):  
Integration Scheme ◽  
Sram Cell

Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate Layer with Vfb controllability

2010 ◽  
Author(s):  
K. Kakushima ◽  
T. Koyanagi ◽  
D. Kitayama ◽  
M. Kouda ◽  
J. Song ◽  
...  
Keyword(s):  
Direct Contact ◽  
Silicate Layer ◽  
Gate Stack ◽  
High K
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