A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology

Author(s):  
A. Bastani ◽  
C.A. Zukowski
2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


2001 ◽  
Author(s):  
S. Maeda ◽  
K. Shiga ◽  
H. Naruoka ◽  
N. Hattori ◽  
T. Iwamatsu ◽  
...  

2001 ◽  
Vol 48 (7) ◽  
pp. 1346-1353 ◽  
Author(s):  
T.B. Hook ◽  
E. Adler ◽  
F. Guarin ◽  
J. Lukaitis ◽  
N. Rovedo ◽  
...  
Keyword(s):  

Author(s):  
S. MOHAN DAS ◽  
GANESH KUMAR M ◽  
BHASKARA RAO K

This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.


2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 1892-1896 ◽  
Author(s):  
Chihoon Lee ◽  
Donggun Park ◽  
Namhyuk Jo ◽  
Chanseong Hwang ◽  
Hyeong Joon Kim ◽  
...  

2005 ◽  
Vol 44 (4B) ◽  
pp. 2125-2131
Author(s):  
Kwang-Seng See ◽  
Wai-Shing Lau ◽  
Suey-Li Toh ◽  
Hong Liao ◽  
Jae Gon Lee ◽  
...  

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