Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology

2006 ◽  
Author(s):  
Tai-Xiang Lai ◽  
Ming-Dou Ker
Keyword(s):  
Integrated Circuits ◽  
Cmos Technology

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

2021 ◽  
Vol 11 (1) ◽  
pp. 6
Author(s):  
Orazio Aiello
Keyword(s):  
Integrated Circuits ◽  
Electromagnetic Interference ◽  
Low Voltage ◽  
Current Source ◽  
Building Blocks ◽  
Cmos Technology ◽  
Threshold Region ◽  
Output Current ◽  
Current Generator ◽  
Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

scholarly journals Impact on Gain and Noise : ECG Amplifier & Comb Filter Design using OTA

2019 ◽  
Vol 8 (6S2) ◽  
pp. 803-808
Keyword(s):  
Integrated Circuits ◽  
Analog Circuit ◽  
Filter Design ◽  
Cmos Technology ◽  
Advanced Technology ◽  
Comb Filter ◽  
Design Environment ◽  
Transistor Channel ◽  
Ecg Amplifier ◽  
Finite Gain

The research paper ventures a novel modelling strategy of finite gain and noise of an electrocardiogram (ECG) amplifier at 0.18, 0.5 and 0.9 micron standard CMOS technologies respectively. An active comb filter is used to design the amplifier for removing the selected frequencies of numerous signals. The presented filter is configured with only Operational Transconductance Amplifiers (OTAs) and capacitors that makes it apt for implementation of monolithic integrated circuits (ICs). The relevance of this analog circuit is verified for a suitable test signal of 60 Hz as in the ECG signal. Using Cadence Virtuoso analog design environment, the effect of transistor channel length and width is examined for analysis of noise and bandwidth. It is observed that the performance in terms of noise and gain considerably increases for advanced technology node. However, for a suitable supply of bias current, a portable ECG system can also provide an improved bandwidth performance of advanced CMOS technology

High Temperature Silicon Carbide CMOS Integrated Circuits

2011 ◽  
Vol 679-680 ◽  
pp. 726-729 ◽  
Author(s):  
David T. Clark ◽  
Ewan P. Ramsay ◽  
A.E. Murphy ◽  
Dave A. Smith ◽  
Robin. F. Thompson ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Band Gap ◽  
High Temperatures ◽  
Wide Band ◽  
Cmos Technology ◽  
Cmos Integrated Circuits ◽  
Wide Band Gap ◽  
Circuit Performance

The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.

Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level

2016 ◽  
Vol 26 (02) ◽  
pp. 1750023
Author(s):  
Minoh Son ◽  
Changkun Park
Keyword(s):  
Integrated Circuits ◽  
Cmos Technology ◽  
Thermal Source ◽  
Esd Protection ◽  
A Cell ◽  
Protection Devices ◽  
Layout Technique ◽  
Typical Layout ◽  
Zigzag Shape ◽  
Survival Level

In this study, we propose cell-based diodes which are laid out with a zigzag shape as electrostatic discharge (ESD) protection elements to enhance the ESD survival level of the diodes. Generally, diodes are regarded as simple ESD protection devices in integrated circuits. During ESD events, the P–N junction of the ESD diode acts as a thermal source. In this study, we investigate a distributed layout method which relies on a cell-based ESD diode to prevent an excessive increase in the temperature at the P–N junction. However, although the distributed layout enhances the ESD survival levels of the ESD diode, the required area increases compared that of a typical layout. Thus, we propose a zigzag layout technique for the cell-based diode to reduce the area and obtain a high ESD survival level. To verify the feasibility of the zigzag layout techniques for cell-based diodes, we designed ESD diodes using 110[Formula: see text]nm RF CMOS technology. The experimental results successfully demonstrate the feasibility of the proposed method.

Linear HgCdTe IR FPA 288×4 with bidirectional scanning

2010 ◽  
Vol 18 (3) ◽  
Author(s):  
V.V. Vasilyev ◽  
A.V. Predein ◽  
V.S. Varavin ◽  
N.N. Mikhailov ◽  
S.A. Dvoretsky ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Bias Voltage ◽  
Differential Resistance ◽  
Cmos Technology ◽  
Inert Atmosphere ◽  
Reverse Bias Voltage ◽  
Zero Bias ◽  
Photosensitive Layer ◽  
Boron Ions ◽  
Dark Currents

AbstractThe long wavelength (8–12 μm) IR FPA 288×4 based on a hybrid assembly of n+-p diode photosensitive arrays (PA) of HgCdTe (MCT) MBE-grown structures and time delay integration (TDI) readout integrated circuits (ROIC) with bidirectional scanning have been developed, fabricated, and investigated. The p-type MCT structures were obtained by thermal annealing of as-grown n-type material in inert atmosphere. The MCT photosensitive layer with the composition 0.20–0.23 of mole fraction of CdTe was surrounded by the wide gap layers to decrease the recombination rate and surface leakage current. The diode arrays were fabricated by planar implantation of boron ions into p-MCT. The typical dark currents were about 4–7 nA at the reverse bias voltage of 150 mV. The differential resistance R was up to R0 = 1.6×107 Ω zero bias voltage, which corresponded to R0A ∼70 Ω ·cm2 and to the maximal value Rmax = 2.1 × 108 Ω. The bidirectional TDI deselecting ROIC was developed and fabricated by 1.0-μm CMOS technology with two metallic and two polysilicon layers.The IR FPAs were free of defect channels and have the average values of responsivity Sλ = 2.27×108 V/W, the detectivity Dλ * = 2.13 × 1011 cm × Hz1/2 × Wt1, and the noise equivalent temperature difference NETD = 9 mK.

LDMOS and LIGT's in CMOS technology for power integrated circuits

1987 ◽  
Author(s):  
S. Mukherjee ◽  
M. Amato ◽  
I. Wacyk ◽  
V. Rumennik
Keyword(s):  
Integrated Circuits ◽  
Cmos Technology

scholarly journals Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

2021 ◽  
Vol 12 (1) ◽  
pp. 215-224
Author(s):  
Mahnoor Maghroori ◽  
Mehdi Dolatshahi
Keyword(s):  
Genetic Algorithms ◽  
Integrated Circuits ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Design Tool ◽  
Optimization Approach ◽  
Multi Objective Optimization ◽  
Multi Objective ◽  
Cmos Vlsi

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

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