Aizup-a pipelined processor design and implementation on XILINX FPGA chip

1996 ◽  
Author(s):  
Yamin Li ◽  
Wanming Chu
Keyword(s):  
Processor Design ◽  
Design And Implementation ◽  
Fpga Chip ◽  
Xilinx Fpga

scholarly journals Analysis of Area-Efficiency vs. Unrolling for eSTREAM Hardware Portfolio Stream Ciphers

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1935
Author(s):  
Fares Alharbi ◽  
Muhammad Khurram Hameed ◽  
Anusha Chowdhury ◽  
Ayesha Khalid ◽  
Anupam Chattopadhyay ◽  
...  
Keyword(s):  
Internet Of Things ◽  
Theoretical Prediction ◽  
High Performance ◽  
Stream Ciphers ◽  
Limited Resources ◽  
Efficient Design ◽  
Low Resource ◽  
Area Efficiency ◽  
Design And Implementation ◽  
Xilinx Fpga

The demand for low resource devices has increased rapidly due to the advancements in Internet-of-things applications. These devices operate in environments that have limited resources. To ensure security, stream ciphers are implemented on hardware due to their speed and simplicity. Amongst different stream ciphers, the eSTREAM ciphers stand due to their frugal implementations. This work probes the effect of unrolling on the efficiency of eSTREAM ciphers, including Trivium, Grain (Grain 80 and Grain 128) and MICKEY (MICKEY 2.0 and MICKEY-128 2.0). It addresses the question of optimal unrolling for designing high-performance stream ciphers. The increase in the area consumption is also bench-marked. The analysis is conducted to identify efficient design principles for ciphers. We experimentally show that the resulting performance after unrolling may disagree with the theoretical prediction when the effects of technology library are considered. We report pre-layout synthesis results on 65 and 130 nm ASIC technology as well as synthesis results for Xilinx FPGA platform in support of our claim. Based on our findings, cipher design and implementation suggestions are proposed to aid hardware designers. Furthermore, we explore why and where area-efficiency for these ciphers saturate.

Design and Implementation of RAM Operation Conflict Arbiter IC in LED/LCD Display Control System

2012 ◽  
Vol 268-270 ◽  
pp. 1574-1577
Author(s):  
Zhao Jie ◽  
Fei Yu ◽  
Jing Xia Wang ◽  
Liu Li
Keyword(s):  
Control System ◽  
Low Cost ◽  
Structure Design ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
System A ◽  
Lcd Display ◽  
Working Principle ◽  
Fpga Chip ◽  
Display Control

To solve the writing and reading operation conflict to RAM in LED/LCD display control system, a new RAM operation conflict arbiter IC was proposed. Comparing the traditional dual ports RAM, the IC has the advantages of low-cost and high stability. By analyzing the working principle and structure design, the IC was designed in pure digital way with Verilog HDL, and passed the simulation verify. Finally the IC was realized by Alter FPGA chip and passed the actual test.

High Speed Federated Filter Design and Implementation

2013 ◽  
Vol 694-697 ◽  
pp. 2535-2539
Author(s):  
K.B Zhang ◽  
J.M Gao ◽  
P.L Jiang
Keyword(s):  
High Speed ◽  
Filter Design ◽  
Integrated Navigation ◽  
Information Distribution ◽  
Simulation Experiments ◽  
Integrated Navigation System ◽  
Design And Implementation ◽  
System A ◽  
Fpga Chip ◽  
Computing Structure

The theory of federal filter based on the Kalman filter is investigated in the design process, as well as the federal filter information distribution. Considering the advantage of parallel computing structure, the FPGA chip is selected and used to realize the IP core encapsulation and design of Federated Filter. The filtering speed is greatly improved to meet federal filter integrated navigation system. A group simulation experiments are conducted. The results shown that the filtering accuracy and filtering time of federal filter are both improved using the proposed method.

Design and Implementation of the Tightly-Coupled SINS / GPS Integrated Navigation System Based on FPGA for Target Missile

2013 ◽  
Vol 313-314 ◽  
pp. 287-290 ◽  
Author(s):  
Jing Jie Guo ◽  
Xiao Feng Cai ◽  
Chao He
Keyword(s):  
Navigation System ◽  
Integrated Control ◽  
Integrated Navigation ◽  
Integrated Navigation System ◽  
Nios Ii ◽  
Navigation Data ◽  
Design And Implementation ◽  
Control Computer ◽  
Tightly Coupled ◽  
Fpga Chip

A novel architecture of tightly-coupled SINS/ GPS integrated navigation system based on FPGA for target missile is proposed in this paper.The whole system is built on a single single FPGA chip containing a Nios II soft-core processor. In addition, the embedded real-time operating system μC/OS-IIis transplanted to the Nios II processor for managing each module in the system. The system can still provide the high-precision navigation data to integrated control computer of target missile when the number of available satellites is less than 4 by means of processing the pseudorange and pseudorange rate seprately. Therefore, the system has the strong application significance in terms of reducing the route shortcut of target missile.

Design and Implementation of Manchester CODEC Based on FPGA

2013 ◽  
Vol 273 ◽  
pp. 805-809 ◽  
Author(s):  
Yun Hua Zuo ◽  
Jun Yang ◽  
Xiao Yu Cheng
Keyword(s):  
Modular Design ◽  
Good Stability ◽  
Parity Check ◽  
Design And Implementation ◽  
Design Scheme ◽  
Baseband Signal ◽  
M Sequence ◽  
Quartus Ii ◽  
Fpga Chip ◽  
Sequence Generator

This paper designed and realized Manchester encoder and decoder based on FPGA. The M sequence generator produced input baseband signal, Manchester CODEC possessed parity check function, and the output signals of encoding and decoding were stable. This design used VHDL language programme, encoder and decoder used modular design, simulated and tested in Altera development software Quartus II 8.0, and downloaded to FPGA chip Cyclone II EP2C35F672C6 for verification. The results showed that the design scheme is good to realize Manchester CODEC, and possesses good stability and reliability.

Sign in / Sign up

Export Citation Format

Share Document