Proceedings of 1994 VLSI Technology Symposium
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Published By IEEE

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A novel disposable post technology for self-aligned sub-micron contacts

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324377 ◽

2002 ◽

Author(s):

M. Cleeves ◽

K. Ramkumar ◽

R. Gettle

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Hydrogen-radical-balanced steam oxidation for growing ultra-thin high-reliability gate oxide films

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324431 ◽

2002 ◽

Cited By ~ 1

Author(s):

K. Ohmi ◽

K. Nakamura ◽

T. Futatsuki ◽

T. Ohmi

Keyword(s):

High Reliability ◽

Oxide Films ◽

Gate Oxide ◽

Steam Oxidation ◽

Hydrogen Radical

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High speed sub-halfmicron flash memory technology with simple stacked gate structure cell

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324381 ◽

2002 ◽

Cited By ~ 5

Author(s):

S. Mori ◽

E. Sakagami ◽

Y. Yamaguchi ◽

E. Kamiya ◽

M. Tanimoto ◽

...

Keyword(s):

Flash Memory ◽

High Speed ◽

Gate Structure

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A low donor concentration retrograde profile Si bipolar transistor for low-temperature BiCMOS LSI's

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324408 ◽

2002 ◽

Author(s):

K. Imai ◽

Y. Kinoshita ◽

T. Yamazaki ◽

T. Tatsumi ◽

T. Tashiro

Keyword(s):

Low Temperature ◽

Bipolar Transistor ◽

Donor Concentration

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1/f noise in poly-Si MOSFET and strong correlation with oxide traps and grain boundaries

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324442 ◽

2002 ◽

Cited By ~ 1

Author(s):

T. Hashimoto ◽

M. Aoki ◽

T. Yamanaka ◽

Y. Kamigaki ◽

T. Nishida

Keyword(s):

Grain Boundaries ◽

Strong Correlation ◽

Oxide Traps

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Precise measurement method of source and drain parasitic resistance and design guideline for scaled MOSFET

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324423 ◽

2002 ◽

Cited By ~ 6

Author(s):

A. Azuma ◽

T. Asamura ◽

Y. Toyoshima ◽

M. Kakumu

Keyword(s):

Measurement Method ◽

Precise Measurement ◽

Design Guideline ◽

Parasitic Resistance

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New buried channel FLASH memory cell with symmetrical source/drain structure for 64 Mbit or beyond

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324373 ◽

2002 ◽

Author(s):

H. Oda ◽

S. Ueno ◽

M. Inuishi ◽

N. Tsubouchi

Keyword(s):

Flash Memory ◽

Memory Cell ◽

Buried Channel ◽

Flash Memory Cell

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Temperature and channel-length dependence of impact ionization in p-channel MOSFETs

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324425 ◽

2002 ◽

Cited By ~ 8

Author(s):

M. Mastrapasqua ◽

J. Bude ◽

M. Pinto ◽

L. Manchanda ◽

K.F. Lee

Keyword(s):

Impact Ionization ◽

Channel Length ◽

Length Dependence

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Ultra-low contact resistance metallization by a silicidation technology employing a silicon capping layer for protection against contamination

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324376 ◽

2002 ◽

Cited By ~ 4

Author(s):

K. Yamada ◽

K. Tomita ◽

T. Ohmi

Keyword(s):

Contact Resistance ◽

Capping Layer

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Novel deep sub-quarter micron PMOSFETs with ultra-shallow junctions utilizing boron diffusion from poly-Si/oxide(BDSOX)

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324397 ◽

2002 ◽

Author(s):

M. Togo ◽

T. Mogami ◽

K. Uwasawa ◽

T. Kunio

Keyword(s):

Boron Diffusion ◽

Shallow Junctions ◽

Ultra Shallow Junctions

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Proceedings of 1994 VLSI Technology SymposiumLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A novel disposable post technology for self-aligned sub-micron contacts

Hydrogen-radical-balanced steam oxidation for growing ultra-thin high-reliability gate oxide films

High speed sub-halfmicron flash memory technology with simple stacked gate structure cell

A low donor concentration retrograde profile Si bipolar transistor for low-temperature BiCMOS LSI's

1/f noise in poly-Si MOSFET and strong correlation with oxide traps and grain boundaries

Precise measurement method of source and drain parasitic resistance and design guideline for scaled MOSFET

New buried channel FLASH memory cell with symmetrical source/drain structure for 64 Mbit or beyond

Temperature and channel-length dependence of impact ionization in p-channel MOSFETs

Ultra-low contact resistance metallization by a silicidation technology employing a silicon capping layer for protection against contamination

Novel deep sub-quarter micron PMOSFETs with ultra-shallow junctions utilizing boron diffusion from poly-Si/oxide(BDSOX)

Proceedings of 1994 VLSI Technology Symposium
Latest Publications