Simulation Study of the Use of AlGaN/GaN Ultra-Thin-Barrier HEMTs with Hybrid Gates for Achieving a Wide Threshold Voltage Modulation Range

In this work, novel hybrid gate Ultra-Thin-Barrier HEMTs (HG-UTB HEMTs) featuring a wide modulation range of threshold voltages (VTH) are proposed. The hybrid gate structure consists of a p-GaN gate part and a MIS-gate part. Due to the depletion effect assisted by the p-GaN gate part, the VTH of HG-UTB HEMTs can be significantly increased. By tailoring the hole concentration of the p-GaN gate, the VTH can be flexibly modulated from 1.63 V to 3.84 V. Moreover, the MIS-gate part enables the effective reduction in the electric field (E-field) peak at the drain-side edge of the p-GaN gate, which reduces the potential gate degradation originating from the high E-field in the p-GaN gate. Meanwhile, the HG-UTB HEMTs exhibit a maximum drain current as high as 701 mA/mm and correspond to an on-resistance of 10.1 Ω mm and a breakdown voltage of 610 V. The proposed HG-UTB HEMTs are a potential means to achieve normally off GaN HEMTs with a promising device performance and featuring a flexible VTH modulation range, which is of great interest for versatile power applications.

A Novel Bidirectional AlGaN/GaN ESD Protection Diode

Despite the superior working properties, GaN-based HEMTs and systems are still confronted with the threat of a transient ESD event, especially for the vulnerable gate structure of the p-GaN or MOS HEMTs. Therefore, there is still an urgent need for a bidirectional ESD protection diode to improve the ESD robustness of a GaN power system. In this study, an AlGaN/GaN ESD protection diode with bidirectional clamp capability was proposed and investigated. Through the combination of two floating gate electrodes and two pF-grade capacitors connected in parallel between anode or cathode electrodes and the adjacent floating gate electrodes (CGA (CGC)), the proposed diode could be triggered by a required voltage and possesses a high secondary breakdown current (IS) in both forward and reverse transient ESD events. Based on the experimental verification, it was found that the bidirectional triggering voltages (Vtrig) and IS of the proposed diode were strongly related to CGA (CGC). With CGA (CGC) increasing from 5 pF to 25 pF, Vtrig and IS decreased from ~18 V to ~7 V and from ~7 A to ~3 A, respectively. The diode’s high performance demonstrated a good reference for the ESD design of a GaN power system.

A 1.2 kV SiC MOSFET with Integrated Heterojunction Diode and P-shield Region

A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time and reverse recovery charge of the IHP-MOSFET decreased by 62.5% and 85.7%, respectively. In addition, a high breakdown voltage (BV) and low maximum oxide electric field (EMOX) could be achieved in the IHP-MOSFET by introducing a p-shield region (PSR) that effectively disperses the electric field in the off-state. The proposed device also exhibited 3.9 times lower gate-to-drain capacitance (CGD) than the C-MOSFET due to the split-gate structure and grounded PSR. As a result, the IHP-MOSFET had electrically excellent static and dynamic characteristics, and the Baliga’s figure of merit (BFOM) and high frequency figure of merit (HFFOM) were increased by 37.1% and 72.3%, respectively. Finally, the switching energy loss was decreased by 59.5% compared to the C-MOSFET.

Design of Hybrid Schottky-Ohmic Gate in Normally-Off p-GaN Gate AlGaN/GaN HEMTs

This study proposes three hybrid Schottky-ohmic gate structures for normally-off p-GaN gate AlGaN/GaN HEMTs. One has a Schottky-gate cover on the ohmic-gate and has part of the area contact to the p-GaN surface at the left and right sides of ohmic-gate (Structure A). The two others only have the Schottky-gate contact to the p-GaN surface at the left side (Structure B) or right side (Structure C) of the ohmic-gate. Different gate metal designs change the hole injection from p-GaN to GaN channel and show various gate leakages. The optimized contact length of Schottky-gate can suppress on-state gate leakage current over two orders of magnitude compared to conventional ohmic p-GaN gate HEMT. The improved on-state maximum drain current is over 60 mA/mm compared to Schottky p-GaN gate HEMT. Optimal performance in Structure B with Schottky-gate contact length ranges from 0.8 to 1.8 μm in a 2 μm gate geometry.

Analysis of Thermal Characteristics of AlGaN/GaN Heterostructure Field-Effect Transistors Using Micro-Raman Spectroscopy

We investigated the heat dissipation in heterostructure field-effect transistors (HFETs) using microRaman measurement of the temperature in active AIGaN/GaN. By varying the gate structure, the heat dissipation through the gate was clearly revealed. The temperature increased to 120 °C at the flat gate device although the inserted gate increased to only 37 °C. Our results showed that the inserted gate structure reduced the self-heating effect by three times compared to the flat gate structure. Temperature mapping using micro-Raman measurement confirmed that the temperature of the near gate area was lower than that of the near drain area. This indicated that the inserted gate electrode structure effectively prohibited self-heating effects.

Forecasting Variation Trends of Stocks via Multiscale Feature Fusion and Long Short-Term Memory Learning

Forecasting stock price trends accurately appears a huge challenge because the environment of stock markets is extremely stochastic and complicated. This challenge persistently motivates us to seek reliable pathways to guide stock trading. While the Long Short-Term Memory (LSTM) network has the dedicated gate structure quite suitable for the prediction based on contextual features, we propose a novel LSTM-based model. Also, we devise a multiscale convolutional feature fusion mechanism for the model to extensively exploit the contextual relationships hidden in consecutive time steps. The significance of our designed scheme is twofold. (1) Benefiting from the gate structure designed for both long- and short-term memories, our model can use the given stock history data more adaptively than traditional models, which greatly guarantees the prediction performance in financial time series (FTS) scenarios and thus profits the prediction of stock trends. (2) The multiscale convolutional feature fusion mechanism can diversify the feature representation and more extensively capture the FTS feature essence than traditional models, which fairly facilitates the generalizability. Empirical studies conducted on three classic stock history data sets, i.e., S&P 500, DJIA, and VIX, demonstrated the effectiveness and stability superiority of the suggested method against a few state-of-the-art models using multiple validity indices. For example, our method achieved the highest average directional accuracy (around 0.71) on the three employed stock data sets.

4-output Programmable Spin Wave Logic Gate

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

4-output Programmable Spin Wave Logic Gate

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

2-output Spin Wave Programmable Logic Gate

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing \{AND, OR, NAND, NOR\} and \{XOR and XNOR\} functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.