An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction

2017 ◽  
pp. 581-593
Author(s):  
Jasmine Kaur Gulati ◽  
Bhanu Prakash ◽  
Sumit Darak
Keyword(s):  
Power Reduction ◽  
Clock Tree

Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes

2014 ◽  
Vol 10 (1) ◽  
pp. 32-37 ◽  
Author(s):  
Biswajit Patra ◽  
Amlan Chakrabarti ◽  
Sanatan Chattopadhyay
Keyword(s):  
Power Reduction ◽  
Clock Tree ◽  
Technology Nodes

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

2011 ◽  
Vol E94-C (3) ◽  
pp. 288-295 ◽  
Author(s):  
Kazuyoshi TAKAGI ◽  
Yuki ITO ◽  
Shota TAKESHIMA ◽  
Masamitsu TANAKA ◽  
Naofumi TAKAGI
Keyword(s):  
Clock Tree ◽  
Clock Tree Synthesis ◽  
Tree Synthesis

Actuator power reduction using L-C oscillator circuits

2000 ◽  
Author(s):  
Jayant Sirohi ◽  
Inderjit Chopra
Keyword(s):  
Power Reduction ◽  
Oscillator Circuits

LEAKAGE POWER REDUCTION USING MULTI MODAL DRIVEN HIERARCHICAL POWER MODE SWITCHES

2018 ◽  
Vol 6 (2) ◽  
pp. 1
Author(s):  
SEKHAR REDDY M. CHANDRA ◽  
REDDY P. RAMANA ◽  
◽  
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Power Mode

Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree

2011 ◽  
Author(s):  
Yu Huang ◽  
Wu-Tung Cheng ◽  
Ting-Pu Tai ◽  
Liyang Lai ◽  
Ruifeng Guo ◽  
...  
Keyword(s):  
Hold Time ◽  
Clock Signal ◽  
Clock Tree ◽  
Scan Testing ◽  
Design Error ◽  
Functional Logic ◽  
Scan Chains ◽  
Delay Defects

Abstract If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

Stand-by Power Reduction Using Experimentally Demonstrated Nano-Electromechanical Switch in CMOS Technologies

2020 ◽  
pp. 1-7
Author(s):  
Sumit Saha ◽  
Arpit Singh ◽  
Maryam Shojaei Baghini ◽  
Mayank Goel ◽  
V. Ramgopal Rao
Keyword(s):  
Power Reduction

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

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