Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.

Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469195 ◽

2005 ◽

Cited By ~ 2

Author(s):

M. Tada ◽

H. Ohtake ◽

M. Narihiro ◽

F. Ito ◽

T. Taiji ◽

...

Keyword(s):

Feasibility Study ◽

Scale Down ◽

Damascene Interconnects

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Novel SiO/sub 2/AlN/HfAlO/IrO/sub 2/ memory with fast erase, large ΔV/sub TH/ and good retention

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469271 ◽

2005 ◽

Cited By ~ 22

Author(s):

C.H. Lai ◽

A. China ◽

K.C. Chiang ◽

W.J. Yoo ◽

C.F. Cheng ◽

...

Keyword(s):

Good Retention

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Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469257 ◽

2005 ◽

Cited By ~ 23

Author(s):

F. Andrieu ◽

T. Ernst ◽

F. Lime ◽

F. Rochette ◽

K. Romanjek ◽

...

Keyword(s):

High Field ◽

Comparative Investigation

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Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469248 ◽

2005 ◽

Cited By ~ 8

Author(s):

Sung-Young Lee ◽

Eun-Jung Yoon ◽

Dong-Suk Shin ◽

Sung-Min Kim ◽

Sung-Dae Suk ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Metal Gate ◽

Power Application

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Stable SRAM cell design for the 32 nm node and beyond

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469239 ◽

2005 ◽

Cited By ~ 250

Author(s):

L. Chang ◽

D.M. Fried ◽

J. Hergenrother ◽

J.W. Sleight ◽

R.H. Dennard ◽

...

Keyword(s):

Cell Design ◽

Sram Cell

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High density and fully compatible embedded DRAM cell with 45nm CMOS technology (CMOS6)

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469193 ◽

2005 ◽

Cited By ~ 3

Author(s):

T. Sanuki ◽

Y. Sogo ◽

A. Oishi ◽

Y. Okayama ◽

R. Hasumi ◽

...

Keyword(s):

Cmos Technology ◽

High Density

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BAVI-cell: a novel high-speed 50 nm SONOS memory with band-to-band tunneling initiated avalanche injection mechanism

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469237 ◽

2005 ◽

Author(s):

Jae Sung Sim ◽

Il Han Park ◽

Seongjae Cho ◽

Tae Hun Kim ◽

Ki Whan Song ◽

...

Keyword(s):

High Speed ◽

Band To Band Tunneling ◽

Injection Mechanism

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A novel NAND-type PHINES nitride trapping storage flash memory cell with physically 2-bits-per-cell storage, and a high programming throughput for mass storage applications

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469234 ◽

2005 ◽

Cited By ~ 5

Author(s):

C.C. Yeh ◽

T. Wang ◽

Y.Y. Liao ◽

W.J. Tsai ◽

T.C. Lu ◽

...

Keyword(s):

Flash Memory ◽

Memory Cell ◽

Mass Storage ◽

Flash Memory Cell ◽

Cell Storage

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Fermi level pinning engineering by Al compositional modulation and doped partial silicide for HfAlO/sub x/(N) CMOSFETs

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469216 ◽

2005 ◽

Cited By ~ 7

Author(s):

M. Kadoshima ◽

A. Ogawa ◽

M. Takahashi ◽

H. Ota ◽

N. Mise ◽

...

Keyword(s):

Fermi Level ◽

Fermi Level Pinning ◽

Compositional Modulation

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High performance FDSOI CMOS technology with metal gate and high-k

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. ◽

10.1109/.2005.1469272 ◽

2005 ◽

Cited By ~ 12

Author(s):

B. Doris ◽

Y.H. Kim ◽

B.P. Linder ◽

M. Steen ◽

V. Narayanan ◽

...

Keyword(s):

High Performance ◽

Cmos Technology ◽

Metal Gate ◽

High K

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Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects

Novel SiO/sub 2/AlN/HfAlO/IrO/sub 2/ memory with fast erase, large ΔV/sub TH/ and good retention

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application

Stable SRAM cell design for the 32 nm node and beyond

High density and fully compatible embedded DRAM cell with 45nm CMOS technology (CMOS6)

BAVI-cell: a novel high-speed 50 nm SONOS memory with band-to-band tunneling initiated avalanche injection mechanism

A novel NAND-type PHINES nitride trapping storage flash memory cell with physically 2-bits-per-cell storage, and a high programming throughput for mass storage applications

Fermi level pinning engineering by Al compositional modulation and doped partial silicide for HfAlO/sub x/(N) CMOSFETs

High performance FDSOI CMOS technology with metal gate and high-k

Export Citation Format

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects

Novel SiO/sub 2/AlN/HfAlO/IrO/sub 2/ memory with fast erase, large ΔV/sub TH/ and good retention

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application

Stable SRAM cell design for the 32 nm node and beyond

High density and fully compatible embedded DRAM cell with 45nm CMOS technology (CMOS6)

BAVI-cell: a novel high-speed 50 nm SONOS memory with band-to-band tunneling initiated avalanche injection mechanism

A novel NAND-type PHINES nitride trapping storage flash memory cell with physically 2-bits-per-cell storage, and a high programming throughput for mass storage applications

Fermi level pinning engineering by Al compositional modulation and doped partial silicide for HfAlO/sub x/(N) CMOSFETs

High performance FDSOI CMOS technology with metal gate and high-k

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.
Latest Publications