This paper presents the novel way to deal with diminish power utilization in a ternary content addressable memory (TCAM) designed in current innovation. The main aim of this TCAM design is to reduce the dynamic power consumption. In TCAM large amount of the power consumption happens during search operation, so we focussed on this area. Here right now give pragmatic plan of a TCAM which is arranged for low-power applications. Simulation of this design has done in Tanned EDA V.16 tool. For simulations of Low power TCAM designs we used predictive technology model (PTM) 45nm for high-performance applications which include metal gate, high-k and stress impact of CMOS technology.
A Power Efficient Improved NOR-Type TCAM Design using OR-Type Match-Line Segment
