Efficient Design Flow for Fixed-Point Systems

Photocatalytic membrane reactors with different configurations (design, flow modes and light sources) have been widely applied for pollutant removal. A thorough understanding of the contribution of reactor design to performance is required to be able to compare photocatalytic materials. Reactors with different flow designs are implemented for process efficiency comparisons. Several figures-of-merit, namely adapted space-time yield (STY) and photocatalytic space-time yield (PSTY), specific energy consumption (SEC) and degradation rate constants, were used to assess the performance of batch, flow-along and flow-through reactors. A fair comparison of reactor performance, considering throughput together with energy efficiency and photocatalytic activity, was only possible with the modified PSTY. When comparing the three reactors at the example of methylene blue (MB) degradation under LED irradiation, flow-through proved to be the most efficient design. PSTY1/PSTY2 values were approximately 10 times higher than both the batch and flow-along processes. The highest activity of such a reactor is attributed to its unique flow design which allowed the reaction to take place not only on the outer surface of the membrane but also within its pores. The enhancement of the mass transfer when flowing in a narrow space (220 nm in flow-through) contributes to an additional MB removal.

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mNet2FPGA: A Design Flow for Mapping a Fixed-Point CNN to Zynq SoC FPGA

Electronics ◽

10.3390/electronics9111823 ◽

2020 ◽

Vol 9 (11) ◽

pp. 1823

Author(s):

Tomyslav Sledevič ◽

Artūras Serackis

Keyword(s):

Neural Networks ◽

Fixed Point ◽

Processing System ◽

Design Flow ◽

Feature Maps ◽

Gate Arrays ◽

The Core ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Fully Connected

The convolutional neural networks (CNNs) are a computation and memory demanding class of deep neural networks. The field-programmable gate arrays (FPGAs) are often used to accelerate the networks deployed in embedded platforms due to the high computational complexity of CNNs. In most cases, the CNNs are trained with existing deep learning frameworks and then mapped to FPGAs with specialized toolflows. In this paper, we propose a CNN core architecture called mNet2FPGA that places a trained CNN on a SoC FPGA. The processing system (PS) is responsible for convolution and fully connected core configuration according to the list of prescheduled instructions. The programmable logic holds cores of convolution and fully connected layers. The hardware architecture is based on the advanced extensible interface (AXI) stream processing with simultaneous bidirectional transfers between RAM and the CNN core. The core was tested on a cost-optimized Z-7020 FPGA with 16-bit fixed-point VGG networks. The kernel binarization and merging with the batch normalization layer were applied to reduce the number of DSPs in the multi-channel convolutional core. The convolutional core processes eight input feature maps at once and generates eight output channels of the same size and composition at 50 MHz. The core of the fully connected (FC) layer works at 100 MHz with up to 4096 neurons per layer. In a current version of the CNN core, the size of the convolutional kernel is fixed to 3×3. The estimated average performance is 8.6 GOPS for VGG13 and near 8.4 GOPS for VGG16/19 networks.

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A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective

Microelectronics Reliability ◽

10.1016/j.microrel.2009.11.015 ◽

2010 ◽

Vol 50 (3) ◽

pp. 424-437 ◽

Cited By ~ 17

Author(s):

Anirban Sengupta ◽

Reza Sedaghat ◽

Zhipeng Zeng

Keyword(s):

Design Space Exploration ◽

Parametric Optimization ◽

Design Space ◽

Space Exploration ◽

Design Flow ◽

High Level Synthesis ◽

Efficient Design ◽

Synthesis Design ◽

Novel Approach ◽

High Level

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PREDICTABILITY IN RT-LEVEL DESIGNS

Journal of Circuits System and Computers ◽

10.1142/s0218126602000483 ◽

2002 ◽

Vol 11 (04) ◽

pp. 323-332 ◽

Cited By ~ 3

Author(s):

ANKUR SRIVASTAVA ◽

EREN KURSUN ◽

MAJID SARRAFZADEH

Keyword(s):

Polynomial Time ◽

Power Dissipation ◽

Polynomial Time Algorithm ◽

Time Algorithm ◽

Primary Objective ◽

Design Flow ◽

Automation System ◽

Efficient Design ◽

Delay Constraints ◽

Future Work

The primary objective of this paper is to provide an initial impetus to predictability driven design flow. Predictability is the quantified form of accuracy. The novelty lies in defining and using the idea of predictability. In order to illustrate the basic concepts we focus on the power estimation problem in RT-Level designs. Our experiments showed that predictability at RT-Level could be improved by making the resource delay constraints more stringent. This procedure may come with increased power dissipation. We present an optimal pseudo-polynomial time algorithm to optimize predictability while keeping the increase in power dissipation within a budget. We further extend this algorithm to generate an ∊-approximate solution in polynomial time where ∊ is a user defined parameter. The algorithm probably generates solutions that differ at-most ∊C max from the optimal. The future work would include extending the concept of predictability to other levels of design flow and other cost function. We envision a design automation system which does effective tradeoff between predictability and cost hence enabling efficient design exploration.

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