scholarly journals Adaptive Bus Encoding Schemes for Power-Efficient Data Transfer in DSM Environments

Author(s):  
Claudia Kretzschmar ◽  
Markus Scheithauer ◽  
Dietmar Mueller
2012 ◽  
Vol E95.D (12) ◽  
pp. 2852-2859
Author(s):  
Yutaka KAWAI ◽  
Adil HASAN ◽  
Go IWAI ◽  
Takashi SASAKI ◽  
Yoshiyuki WATASE
Keyword(s):  

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption


2012 ◽  
pp. 502-516
Author(s):  
Muzhou Xiong ◽  
Hai Jin

In this chapter, two algorithms have been presented for supporting efficient data transfer in the Grid environment. From a node’s perspective, a multiple data transfer channel can be formed by selecting some other nodes as relays in data transfer. One algorithm requires the sender to be aware of the global connection information while another does not. Experimental results indicate that both algorithms can transfer data efficiently under various circumstances.


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