Investigation of Lattice Surface Layers by Scanning Probe Microscopy

1993 ◽  
pp. 243-256
Author(s):  
Max Firtel ◽  
Gordon Southam ◽  
Terry J. Beveridge ◽  
Wei Xu ◽  
Manfred H. Jericho ◽  
...  
Keyword(s):  
Scanning Probe Microscopy ◽  
Scanning Probe ◽  
Surface Layers ◽  
Probe Microscopy ◽  
Lattice Surface

The Role of Scanning Probe Microscopy in Drug Delivery Research

1996 ◽  
Vol 13 (3-4) ◽  
pp. 225-256 ◽  
Author(s):  
Kevin M. Shakesheff ◽  
Martyn C. Davies ◽  
Clive J. Roberts ◽  
Saul J. B. Tendler ◽  
Philip M. Williams
Keyword(s):  
Drug Delivery ◽  
Scanning Probe Microscopy ◽  
Scanning Probe ◽  
Probe Microscopy

Extending Electrical Scanning Probe Microscopy Measurements of Semiconductor Devices Using Microwave Impedance Microscopy

2015 ◽  
Author(s):  
Benedict Drevniok ◽  
St. John Dixon-Warren ◽  
Oskar Amster ◽  
Stuart L Friedman ◽  
Yongliang Yang
Keyword(s):  
Scanning Probe Microscopy ◽  
Semiconductor Devices ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Scanning Probe ◽  
Cross Sectional ◽  
Probe Microscopy ◽  
Dopant Profiling ◽  
Capacitance Voltage

Abstract Scanning microwave impedance microscopy was used to analyze a CMOS image sensor sample to reveal details of the dopant profiling in planar and cross-sectional samples. Sitespecific capacitance-voltage spectroscopy was performed on different regions of the samples.

Cross-Section Sample Preparation Method for Imaging Dopant Related Anomalies Using Scanning Probe Microscopy Techniques

2014 ◽  
Author(s):  
Swaminathan Subramanian ◽  
Khiem Ly ◽  
Tony Chrastecky
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Section ◽  
Scanning Probe Microscopy ◽  
Preparation Method ◽  
Fault Isolation ◽  
Scanning Probe ◽  
Sample Preparation Method ◽  
Probe Microscopy ◽  
Section Sample

Abstract Visualization of dopant related anomalies in integrated circuits is extremely challenging. Cleaving of the die may not be possible in practical failure analysis situations that require extensive electrical fault isolation, where the failing die can be submitted of scanning probe microscopy analysis in various states such as partially depackaged die, backside thinned die, and so on. In advanced technologies, the circuit orientation in the wafer may not align with preferred crystallographic direction for cleaving the silicon or other substrates. In order to overcome these issues, a focused ion beam lift-out based approach for site-specific cross-section sample preparation is developed in this work. A directional mechanical polishing procedure to produce smooth damage-free surface for junction profiling is also implemented. Two failure analysis applications of the sample preparation method to visualize junction anomalies using scanning microwave microscopy are also discussed.

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