A Novel Sample Preparation Approach for Dopant Profiling of 14 nm FinFET Devices with Scanning Capacitance Microscopy

Three-dimensional device (FinFET) doping requirements are challenging due to fin sidewall doping, crystallinity control, junction profile control, and leakage control in the fin. In addition, physical failure analyses of FinFETs can frequently reach a “dead end” with a No Defect Found (NDF) result when channel doping issues are the suspected culprit (e.g., high Vt, low Vt, low gain, sub-threshold leakage, etc.). In new technology development, the lack of empirical dopant profile data to support device and process models and engineering has had, and continues to have, a profound negative impact on these emerging technologies. Therefore, there exists a critical need for dopant profiling in the industry to support the latest technologies that use FinFETs as their fundamental building block [1]. Here, we discuss a novel sample preparation method for cross-sectional dopant profiling of FinFET devices. Our results show that the combination of low voltage (<500eV), shallow angle (~10 degree) ion milling, dry etching, and mechanical polishing provides an adequately smooth surface (Rq<5Å) and minimizes surface amorphization, thereby allowing a strong Scanning Capacitance Microscopy (SCM) signal representative of local active dopant (carrier) concentration. The strength of the dopant signal was found to be dependent upon mill rate, electrical contact quality, amorphous layer presence and SCM probe quality. This paper focuses on a procedure to overcome critical issues during sample preparation for dopant profiling in FinFETs.

An Improved STEM/EDX Quantitative Method for Dopant Profiling at the Nanoscale

In this paper, an improved quantification technique for STEM/EDX measurements of 1D dopant profiles based on the Cliff-Lorimer equation is presented. The technique uses an iterative absorption correction procedure based on density models correlating the local mass density and composition of the specimen. Moreover, a calibration and error estimation procedure based on linear regression and error propagation is proposed in order to estimate the total measurement error in the dopant density. The proposed approach is applied to the measurement of the As profile in a nanodevice test structure. For the calibration, two crystalline Si specimens implanted with different As doses have been used, and the calibration of the Cliff-Lorimer coefficients has been carried out using Rutherford Back Scattering measurements. The As profile measurement has been carried out on an FinFET test structure, showing that quantitative results can be obtained in the nanometer scale and for dopant atomic densities lower than 1%. Using the proposed approach, the measurement error and detection limit for our experimental setup are calculated and the possibility to improve this limit by increasing the observation time is discussed.

2D carrier Density Mapping Using SNDM-dC/dV and dC/dz of SiC Power MOSFET

Scanning nonlinear dielectric microscopy is continuously developed as an AFM-derived method for 2D dopant profiling of semiconductor devices. In this paper, the authors apply 2D carrier density mapping to Si and SiC and succeed a high resolution observation of the SiC planar power MOSFET. Furthermore, they develop software that combines dC/dV and dC/dz images and expresses both density and polarity in a single distribution image. The discussion provides the details of AFM experiments that were conducted using a Hitachi environmental control AFM5300E system. The results indicated that the carrier density decreases in the boundary region between n plus source and p body. The authors conclude that although the resolutions of dC/dV and dC/dz are estimated to be 20 nm or less and 30 nm or less, respectively, there is a possibility that the resolution can be further improved by using a sharpened probe.

Carrier Depletion near the Grain Boundary of a SiC Bicrystal

Silicon carbide (SiC) bicrystals were prepared by diffusion bonding, and their grain boundary was observed using scanning transmission electron microscopy. The n-type electrical conductivity of a SiC single crystal was confirmed by scanning nonlinear dielectric microscopy (SNDM). Dopant profiling of the sample by SNDM showed that the interface acted as an electrical insulator with a ~2-μm-thick carrier depletion layer. The carrier depletion layer contained a higher number of oxygen impurities than the bulk crystals due to the incorporation of oxygen from the native oxide film during diffusion bonding. Density functional theory calculations of the density of states as a function of the bandgap also supported these findings. The existence of a carrier depletion layer was also confirmed in a p-type polycrystalline SiC ceramic. These results suggest that the electrical conductivity of SiC ceramics was mostly affected by carrier depletion near the grain boundary rather than the grain boundary itself.