CMOS Exclusive-OR (EXOR) gate implementation using conventional logic structures results in high hardware cost and long propagation delay, making it unattractive to logic designers. A number of more efficient two-input CMOS EXOR-gate structures with only six transistors have been proposed in the past. In many applications, such as parity generator, checker, and Exclusive-OR Sum-of-Product (ESOP) circuits, multiple-input EXOR circuits are required. Two kinds of multiple-input EXOR circuit structures are presented, which are smaller, faster, and more power-saving than those formed by simply connecting two-input EXOR gates in a conventional way. The proposed structures are shown to be suitable for ESOP circuits in which four transistors can be saved for each product term. The reduction in area and power makes them attractive for low-power required applications such as mobile computing and wireless communications.
Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications
