The Future of Ultra-Low Power SOTB CMOS Technology and Applications

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [Formula: see text] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[Formula: see text][Formula: see text]m CMOS technology achieves 95.98[Formula: see text]dB peak signal-to-noise and distortion (SNDR) for 10[Formula: see text]KHz signal bandwidth and dissipates 44[Formula: see text][Formula: see text]w while its FOM is obtained about 43 fJ/conv.-step.

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What's cool for the future of ultra low power designs?

Proceedings of the 47th Design Automation Conference on - DAC '10 ◽

10.1145/1837274.1837403 ◽

2010 ◽

Cited By ~ 1

Author(s):

Nagaraj NS ◽

John Byler ◽

Koorosh Nazifi ◽

Venugopal Puvvada ◽

Toshiyuki Saito ◽

...

Keyword(s):

Low Power ◽

Ultra Low Power ◽

The Future

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A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2007.907996 ◽

2008 ◽

Vol 43 (1) ◽

pp. 172-179 ◽

Cited By ~ 49

Author(s):

Yih Wang ◽

Hong Jo Ahn ◽

Uddalak Bhattacharya ◽

Zhanping Chen ◽

Tom Coan ◽

...

Keyword(s):

Low Power ◽

Mobile Applications ◽

Cmos Technology ◽

Ultra Low Power ◽

Leakage Reduction ◽

Sram Design ◽

Low Power Cmos

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Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽

10.1108/cw-09-2019-0127 ◽

2020 ◽

Vol 46 (3) ◽

pp. 183-192

Author(s):

Muhammad Yasir Faheem ◽

Shun'an Zhong ◽

Xinghua Wang ◽

Muhammad Basit Azeem

Keyword(s):

Low Power ◽

Energy Efficient ◽

Supply Voltage ◽

Main Idea ◽

Cost Effective ◽

Cmos Technology ◽

Sar Adc ◽

Ultra Low Power ◽

Content Type ◽

Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

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