Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Work Load ◽  
Input Voltage ◽  
Sar Adc ◽  
Power Circuit ◽  
Ultra Low Power ◽  
Content Type ◽  
Number Of Components

Purpose There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC. Design/methodology/approach The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design. Findings The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step. Originality/value The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Muhammad Basit Azeem ◽  
Xinghua Wang
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Bone Block ◽  
Technological Advancement ◽  
Left Wing ◽  
Ultra Low Power ◽  
Content Type

Purpose Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs. Design/methodology/approach To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library. Findings The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively. Originality/value Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime

2016 ◽  
pp. 78-123
Author(s):  
Priya Gupta ◽  
Anu Gupta ◽  
Abhijit Asati
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Ultra Low Power ◽  
Ripple Carry Adder ◽  
Power Delay Product ◽  
Threshold Regime

In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adders, full adders and partial product generate units have been analyzed for sub-threshold operation. At the last stage ripple carry adder is used in both multipliers. The performance metrics considered for the analysis of the multipliers are: power, delay and PDP. Simulation studies are carried out for 8x8-bit and 16x16-bit input data width. The proposed circuits show energy efficient results with Spectre simulations for the TSMC 180nm CMOS technology at 0.4V supply voltage. The proposed multipliers so implemented outperform its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional multipliers.

An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure

2019 ◽  
Vol 28 (10) ◽  
pp. 1950172
Author(s):  
Mehdi Bandali ◽  
Alireza Hassanzadeh ◽  
Masoume Ghashghaie ◽  
Omid Hashemipour
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Current Steering ◽  
Ultra Low Power ◽  
Current Cell ◽  
Sample Rate

In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[Formula: see text]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [Formula: see text]-V supply voltage with the sample rate of 140[Formula: see text]MS/s show SFDR [Formula: see text] 64.37[Formula: see text]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.

scholarly journals Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8302
Author(s):  
Cancio Monteiro ◽  
Yasuhiro Takahashi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Process Variations ◽  
Cmos Technology ◽  
Process Technology ◽  
Two Phase ◽  
Ultra Low Power ◽  
Ambient Temperatures

Low-power and secure crypto-devices are in crucial demand for the current emerging technology of the Internet of Things (IoT). In nanometer CMOS technology, the static and dynamic power consumptions are in a very critical challenge. Therefore, the FinFETs is an alternative technology due to its superior attributes of non-leakage power, intra-die variability, low-voltage operation, and lower retention voltage of SRAMs. In this study, our previous work on CMOS two-phase clocking adiabatic physical unclonable function (TPCA-PUF) is evaluated in a FinFET device with a 4-bits PUF circuit complexity. The TPCA-PUF-based shorted-gate (SG) and independent-gate (IG) modes of FinFETs are investigated under various ambient temperatures, process variations, and ±20% of supply voltage variations. To validate the proposed TPCA-PUF circuit, the QUALPFU-based Fin-FETs are compared in terms of cyclical energy dissipation, the security metrics of the uniqueness, the reliability, and the bit-error-rate (BER). The proposed TPCA-PUF is simulated using 45 nm process technology with a supply voltage of 1 V. The uniqueness, reliability, and the BER of the proposed TPCA-PUF are 50.13%, 99.57%, and 0.43%, respectively. In addition, it requires a start-up power of 18.32 nW and consumes energy of 2.3 fJ/bit/cycle at the reference temperature of 27 °C.

The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology

2016 ◽  
pp. 229-251
Author(s):  
Kavyashree P. ◽  
Siva S. Yellampalli
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Low Voltage Operation ◽  
Common Gate ◽  
Low Power Cmos ◽  
Power Application

In this chapter, an ultra low power CMOS Common Gate LNA (CGLNA) with a Capacitive Cross-Coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the Noise Figure (NF) and power dissipation. In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCC-CGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.

A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter

2015 ◽  
Vol 24 (08) ◽  
pp. 1550124 ◽  
Author(s):  
Majid Moghaddam ◽  
Mohammad Hossein Moaiyeri ◽  
Mohammad Eshghi ◽  
Ali Jalali
Keyword(s):  
Low Power ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Voltage Level ◽  
Ultra Low Power ◽  
Static Power ◽  
Level Converter ◽  
Low Power Multiplier

This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V DDL , V DDH ) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.

scholarly journals Energy Efficient Bandgap Reference Generator for RFID Transponder EEPROM in 130 nm CMOS Process

2019 ◽  
Vol 8 (4) ◽  
pp. 6422-6426
Keyword(s):  
Low Power ◽  
Radio Frequency Identification ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Reducing Power ◽  
Cmos Technology ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Internal Reference ◽  
Power Supply Voltage

Reducing power dissipation of any circuit can make that circuit more energy-efficient and at the same time promise stability. Recent researchers mainly focus on controlling and monitoring low power designs for different low power applications, wireless systems such as radio frequency identification (RFID) transponder. Therefore, generating an internal reference voltage (VR) for the power management unit is the key challenges for researchers to design such applications. Bandgap reference (BGR) is an essential module that assures temperature and independent VR supply in analog circuits. In this research, an improved BGR is designed with the self-startup circuit, bandgap core and an operational amplifier (OP-AMP) to generate a stable VR. A low-power BGR is simulated using Silterra 130 nm CMOS technology. The designed BGR generates a VR of 1.1 V and consumes only 1.4 µA power form 1.2 V power supply voltage. Moreover, it has a temperature coefficient of 41.6 ppm/℃.

scholarly journals Low Power and Area Efficient 4-2 Compressor for Signal Processing Applications

2020 ◽  
Vol 4 (7) ◽  
pp. 8-13
Author(s):  
Mohan Das S ◽  
Ganesh Kumar M ◽  
Shireesha G
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
Energy Efficient ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Average Power ◽  
Cmos Technology ◽  
Fir Filter ◽  
Area Efficient

In this paper, two performance metrics power and delay are estimated for various XOR-XNOR circuits and Multiplexer for designing 4-2 compressor. The main objective is to design an energy efficient compressor for computing applications in FIR filter. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 4-2 compressors consist of six blocks out of which two XOR-XNOR blocks and four MUX blocks. The average power, delay and energy consumed by the proposed compressor which is based on 5T XOR-XNOR and GDIMUX design is 85.72 nW, 62.53 pS and 5.36 aJ respectively

ANALYSIS OF POWER CONSUMPTION SAR-ADC DYNAMIC COMPARATOR

2016 ◽  
Vol 78 (5-9) ◽  
Author(s):  
Julie R. Rusli ◽  
Noor Shelida Salleh ◽  
Masnita M. Isa ◽  
KY Tan ◽  
Suhaidi Shafie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Cmos Technology ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Regeneration Time ◽  
Dynamic Comparators ◽  
Reset Time

Due to the high demand of ultra-low power in digital application, the needs of energy efficient analog-to-digital converter (ADC) are really essential. The comparator being an important part of successive approximation register (SAR)-ADC needs to have optimum performance under low power condition. This paper presents the comparison on power consumption together with the output performance flow power SAR-ADC dynamic comparators from three different design proposed by previous researchers. The three circuits is simulated and compared in terms of power consumption, regeneration time, reset time and output transient.  The simulation is using Cadence Spectre and setup with 0.18µm CMOS technology, VDD at 0.8V and clock speed 2 at MHz.  The analysis results obtained provides the lowest voltage input different (ΔVin) possible for double tail dynamic comparator using 0.18µm CMOS technology while adhering to the 45 corner process requirement.  The results can be used as references for further design of ultra-low power dynamic comparator.

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