A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

We present three ultra-low-power CMOS circuits: a temperature sensor, a voltage reference and a comparator developed for an ultra-low-power microsystem (ULP-MST) aiming at temperature sensing in harsh environments. The microsystem has 3 main functions: detecting a user-defined temperature threshold T0, generating a wake-up signal that turns on a data-acquisition microprocessor (located in a safe area) above T0, and measuring temperatures above T0. To achieve ultra-low-power operation, the three CMOS circuits are implemented in Silicon-on-Insulator (SOI) CMOS technology and are optimized to work in the subthreshold regime of the transistors. Since our application is mainly for harsh environment (i.e. high temperature and radiation), the chip has been designed using a suitable 1-μm SOI-CMOS technology. Simulations have been performed over the different process corners to verify functionality after fabrication. The typical power dissipation at high temperature (up to 240°C) is less than 100 μW at 5 V supply voltage. Measurements have validated correct operation in the temperature range from −40°C to 300°C before radiation and to 125°C after radiation up to now which will be extended further with a new set-up. Irradiation has been performed from 10 to 30 kGy. Such very high doses cause a shift down of output voltage values, which leads to a change of the temperature detection level and also increases the power dissipation by up to six times. Annealing effects help the partial recovery of the device operation at high temperature and the remote microprocessor enables calibration after radiation to readjust the temperature detection level.

Download Full-text

Stanford's ultra-low-power CMOS technology and applications

Low-power HF Microelectronics: a unified approach ◽

10.1049/pbcs008e_ch3 ◽

2011 ◽

pp. 85-138 ◽

Cited By ~ 20

Author(s):

James Burr ◽

Zongjian Chen ◽

Bevan Baas

Keyword(s):

Low Power ◽

Cmos Technology ◽

Ultra Low Power ◽

Low Power Cmos

Download Full-text

The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology

Advances in Computer and Electrical Engineering - Design and Modeling of Low Power VLSI Systems ◽

10.4018/978-1-5225-0190-9.ch009 ◽

2016 ◽

pp. 229-251

Author(s):

Kavyashree P. ◽

Siva S. Yellampalli

Keyword(s):

Low Power ◽

Low Voltage ◽

Noise Figure ◽

Supply Voltage ◽

Cmos Technology ◽

Ultra Low Power ◽

Low Voltage Operation ◽

Common Gate ◽

Low Power Cmos ◽

Power Application

In this chapter, an ultra low power CMOS Common Gate LNA (CGLNA) with a Capacitive Cross-Coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the Noise Figure (NF) and power dissipation. In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCC-CGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.

Download Full-text

multiPULPly

ACM Journal on Emerging Technologies in Computing Systems ◽

10.1145/3432815 ◽

2021 ◽

Vol 17 (2) ◽

pp. 1-27

Author(s):

Adi Eliahu ◽

Ronny Ronen ◽

Pierre-Emmanuel Gaillardon ◽

Shahar Kvatinsky

Keyword(s):

Neural Network ◽

Power Consumption ◽

Power Systems ◽

Low Power ◽

Network Inference ◽

Cmos Technology ◽

Ultra Low Power ◽

Network Applications ◽

Low Power Cmos ◽

Neural Network Applications

Computationally intensive neural network applications often need to run on resource-limited low-power devices. Numerous hardware accelerators have been developed to speed up the performance of neural network applications and reduce power consumption; however, most focus on data centers and full-fledged systems. Acceleration in ultra-low-power systems has been only partially addressed. In this article, we present multiPULPly, an accelerator that integrates memristive technologies within standard low-power CMOS technology, to accelerate multiplication in neural network inference on ultra-low-power systems. This accelerator was designated for PULP, an open-source microcontroller system that uses low-power RISC-V processors. Memristors were integrated into the accelerator to enable power consumption only when the memory is active, to continue the task with no context-restoring overhead, and to enable highly parallel analog multiplication. To reduce the energy consumption, we propose novel dataflows that handle common multiplication scenarios and are tailored for our architecture. The accelerator was tested on FPGA and achieved a peak energy efficiency of 19.5 TOPS/W, outperforming state-of-the-art accelerators by 1.5× to 4.5×.

Download Full-text