Deterministic transfer of optical-quality carbon nanotubes for atomically defined technology

When continued device scaling reaches the ultimate limit imposed by atoms, technology based on atomically precise structures is expected to emerge. Device fabrication will then require building blocks with identified atomic arrangements and assembly of the components without contamination. Here we report on a versatile dry transfer technique for deterministic placement of optical-quality carbon nanotubes. Single-crystalline anthracene is used as a medium which readily sublimes by mild heating, leaving behind clean nanotubes and thus enabling bright photoluminescence. We are able to position nanotubes of a desired chirality with a sub-micron accuracy under in-situ optical monitoring, thereby demonstrating deterministic coupling of a nanotube to a photonic crystal nanobeam cavity. A cross junction structure is also designed and constructed by repeating the nanotube transfer, where intertube exciton transfer is observed. Our results represent an important step towards development of devices consisting of atomically precise components and interfaces.

Graphene-based 3D XNOR-VRRAM with ternary precision for neuromorphic computing

Recent studies on neural network quantization have demonstrated a beneficial compromise between accuracy, computation rate, and architecture size. Implementing a 3D Vertical RRAM (VRRAM) array accompanied by device scaling may further improve such networks’ density and energy consumption. Individual device design, optimized interconnects, and careful material selection are key factors determining the overall computation performance. In this work, the impact of replacing conventional devices with microfabricated, graphene-based VRRAM is investigated for circuit and algorithmic levels. By exploiting a sub-nm thin 2D material, the VRRAM array demonstrates an improved read/write margins and read inaccuracy level for the weighted-sum procedure. Moreover, energy consumption is significantly reduced in array programming operations. Finally, an XNOR logic-inspired architecture designed to integrate 1-bit ternary precision synaptic weights into graphene-based VRRAM is introduced. Simulations on VRRAM with metal and graphene word-planes demonstrate 83.5 and 94.1% recognition accuracy, respectively, denoting the importance of material innovation in neuromorphic computing.

Impact of device scaling on the electrical properties of MoS2 field-effect transistors

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

Challenges and Solutions of Replacement Metal Gate Patterning to Enable Gate-all-Around Device Scaling

This paper addresses challenges and solutions of replacement metal gate of gate-all-around nanosheet devices. The unit process and integration solutions for the metal gate patterning as well as interface dipole patterning to offer multiple threshold voltage have been developed. The challenges of long channel device integration are also discussed.

Impact of Device Scaling on the Electrical Properties of MoS2 Field-effect Transistors

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with Silicon gate-all-around devices.

Hardware/Software Codesign for Energy Efficiency and Robustness: From Error-Tolerant Computing to Approximate Computing

Voltage scaling, as the most important knob for energy efficiency, is limited by leakage and variability. Variability is arisen from various sources including static manufacturing process, dynamic voltage and temperature fluctuations, and temporal changes over time. To address these variations, designers resort to excessive margins. These margins are increasing rapidly and eventually obliterating any gains due to device scaling. As a consequence, reduction of margins in design has become an important research challenge. We demonstrate how to recover part of these margins through hardware/software codesign with examples in many-core GPUs and FPGAs. This naturally leads to a departure from traditional error-tolerant computing to approximate computing.