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Delay Testing Based on Multiple Faulty Behaviors
VLSI-SoC: Design for Reliability, Security, and Low Power - IFIP Advances in Information and Communication Technology
◽
10.1007/978-3-319-46097-0_5
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2016
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pp. 87-108
Author(s):
Masahiro Fujita
Keyword(s):
Delay Testing
Download Full-text
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References
Structural delay testing of latch-based high-speed pipelines with time borrowing
International Test Conference, 2003. Proceedings. ITC 2003.
◽
10.1109/test.2003.1271097
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2004
◽
Cited By ~ 7
Author(s):
Kun Young Chung
◽
S.K. Gupta
Keyword(s):
High Speed
◽
Delay Testing
◽
Time Borrowing
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BIST test pattern generators for stuck-open and delay testing
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC
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10.1109/edtc.1994.326862
◽
2002
◽
Cited By ~ 22
Author(s):
C.-A. Chen
◽
S.K. Gupta
Keyword(s):
Test Pattern
◽
Delay Testing
◽
Pattern Generators
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Small delay testing for TSVs in 3-D ICs
Proceedings of the 49th Annual Design Automation Conference on - DAC '12
◽
10.1145/2228360.2228546
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2012
◽
Cited By ~ 18
Author(s):
Shi-Yu Huang
◽
Yu-Hsiang Lin
◽
Kun-Han (Hans) Tsai
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Wu-Tung Cheng
◽
Stephen Sunter
◽
...
Keyword(s):
Delay Testing
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Small Delay
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Delay testing considering power supply noise effects
International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)
◽
10.1109/test.1999.805629
◽
2003
◽
Cited By ~ 24
Author(s):
A. Krstic
◽
Yi-Min Jiang
◽
Kwang-Ting Cheng
Keyword(s):
Power Supply
◽
Delay Testing
◽
Power Supply Noise
◽
Noise Effects
◽
Supply Noise
Download Full-text
Design of Single-Event Tolerant Latches in 65nm CMOS Technology for Enhanced Scan Delay Testing
2017 Prognostics and System Health Management Conference (PHM-Harbin)
◽
10.1109/phm.2017.8079149
◽
2017
◽
Author(s):
Chunhua Qi
◽
Liyi Xiao
◽
Tianqi Wang
◽
Mingjiang Wang
Keyword(s):
Cmos Technology
◽
Delay Testing
◽
Single Event
Download Full-text
On-line delay testing of digital circuits
Proceedings of IEEE VLSI Test Symposium
◽
10.1109/vtest.1994.292318
◽
2002
◽
Cited By ~ 44
Author(s):
P. Franco
◽
E.J. McCluskey
Keyword(s):
Digital Circuits
◽
Delay Testing
◽
On Line
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In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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10.1109/tvlsi.2012.2187543
◽
2013
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Vol 21
(3)
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pp. 443-453
◽
Cited By ~ 23
Author(s):
Jhih-Wei You
◽
Shi-Yu Huang
◽
Yu-Hsiang Lin
◽
Meng-Hsiu Tsai
◽
Ding-Ming Kwai
◽
...
Keyword(s):
Sensitivity Analysis
◽
Delay Testing
◽
In Situ Method
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Delay Testing
System-on-Chip Test Architectures
◽
10.1016/b978-012373973-5.50011-5
◽
2008
◽
pp. 263-306
◽
Cited By ~ 1
Author(s):
Duncan M. (Hank) Walker
◽
Michael S. Hsiao
Keyword(s):
Delay Testing
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A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing
2011 Sixteenth IEEE European Test Symposium
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10.1109/ets.2011.21
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2011
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Cited By ~ 8
Author(s):
M. Valka
◽
A. Bosio
◽
L. Dilillo
◽
P. Girard
◽
S. Pravossoudovitch
◽
...
Keyword(s):
Delay Testing
◽
Test Power
◽
Power Limits
◽
Power Evaluation
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Delay Testing Quality in Timing-Optimized Designs
1991, Proceedings. International Test Conference
◽
10.1109/test.1991.519756
◽
2005
◽
Cited By ~ 11
Author(s):
Eun Sei Park
◽
B. Underwood
◽
T.W. Williams
◽
M.R. Mercer
Keyword(s):
Delay Testing
Download Full-text
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