High-Speed Software Implementation of the Optimal Ate Pairing over Barreto–Naehrig Curves

2010 ◽  
pp. 21-39 ◽  
Author(s):  
Jean-Luc Beuchat ◽  
Jorge E. González-Díaz ◽  
Shigeo Mitsunari ◽  
Eiji Okamoto ◽  
Francisco Rodríguez-Henríquez ◽  
...  
Keyword(s):  
High Speed ◽  
Software Implementation ◽  
Ate Pairing

Algorithm for optimal allocation of limited resources based on the game iteration method

2019 ◽  
pp. 89-99
Author(s):  
V. Ya. Vilisov
Keyword(s):  
Optimal Control ◽  
Linear Programming ◽  
Embedded Systems ◽  
Iterative Method ◽  
High Speed ◽  
Optimal Allocation ◽  
Software Implementation ◽  
Limited Resources ◽  
Matrix Game ◽  
Acceptable Accuracy

The article proposes an algorithm for solving a linear programming problem (LPP) based on the use of its representation in the form of an antagonistic matrix game and the subsequent solution of the game by an iterative method. The algorithm is implemented as a computer program. The rate of convergence of the estimates of the solution to the actual value with the required accuracy has been studied. The software implementation shows a high speed of obtaining the LPP solution with acceptable accuracy in fractions or units of seconds. This allows the use algorithm in embedded systems for optimal control.

High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA

2017 ◽  
Vol 15 (05) ◽  
pp. 1750047 ◽  
Author(s):  
S. S. Divakara ◽  
Sudarshan Patilkulkarni ◽  
Cyril Prasanna Raj
Keyword(s):  
Systolic Array ◽  
High Speed ◽  
Parallel Architecture ◽  
Software Implementation ◽  
Wavelet Filter ◽  
Image Transformation ◽  
Complex Wavelet Transform ◽  
Pipelined Architecture ◽  
Array Architecture ◽  
Processing Architecture

In this paper, systolic array-based novel architecture for dual-tree complex wavelet transform (DTCWT) computation is designed and implemented on FPGA. The wavelet filter coefficients of DTCWT are quantized and rounded to nearest integer and the loss in rounding and quantization is limited to 0.5[Formula: see text]dB as compared with software implementation. The parallel architecture designed computes row elements simultaneously and pipelined architecture is designed to compute column elements. The proposed architecture is modeled using Verilog and implemented on Xilinx Virtex II FPGA. For 2D implementation, the design operates at a maximum frequency of 156[Formula: see text]MHz and consumes power less than 3[Formula: see text]W. This is the first design with systolic array architecture on FPGA for DTCWT computation operating at frequencies greater than 100[Formula: see text]MHz.

scholarly journals SOFTWARE IMPLEMENTATION OF THE ARTIFICIAL NEURAL NETWORK FOR VIRTUAL OBJECTS СONTROL

2018 ◽  
pp. 72-78 ◽  
Author(s):  
Yu. B. Popova ◽  
S. V. Yatsynovich
Keyword(s):  
Neural Network ◽  
Mathematical Modeling ◽  
Artificial Neural Network ◽  
High Speed ◽  
Back Propagation ◽  
Computer Game ◽  
Training Sample ◽  
Software Implementation ◽  
Virtual Objects ◽  
Artificial Neural

Artificial neural networks (ANN) are now widely used in control and forecasting problems. The purpose of this work is the implementation of an artificial neural network for virtual objects control in a computer game of football. To achieve this goal, it is necessary to solve a number of problems related to mathematical modeling of ANN, algorithmization and software implementation. The paper deals with the mathematical modeling of an artificial neural network by the method of back propagation of an error, the algorithms for calculating neurons and for teaching ANN are presented. The software implementation of the artificial neural network was performed in the JavaScript language using the Node. js library, which assumed the role of a server for managing the game process. Some functions of the Underscore. js library were used to work with data arrays. The training sample consisted of more than 1000 sets of inputs and outputs, reflecting all possible situations. The results of software implementation of an artificial neural network are described on the example of virtual players control for a computer game. The results of the work show that ANN with a sufficiently high speed in real time gives the necessary direction for the player’s movement. The use of an artificial neural network has reduced the use of CPU time, which is extremely important in problems where rapid decision making is required, because complex calculations and prediction algorithms can not always be invested in 20 ms, which is fraught with skipping moves and losses. The simulated artificial neural network and the implemented algorithm of its learning can be used to solve other problems, for which only new data of the surrounding world are needed.

scholarly journals FPGA Implementation of DTCWT and PCA Based Watermarking Technique

2018 ◽  
Vol 7 (2) ◽  
pp. 82
Author(s):  
M. S. Sudha ◽  
T. C. Thanuja
Keyword(s):  
Wavelet Transform ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Implementation ◽  
Image Watermarking ◽  
Software Implementation ◽  
Low Power Consumption ◽  
Complex Wavelet Transform ◽  
System Generator ◽  
Field Programmable

The hardware implementation of the image watermarking algorithm offers numerous distinct advantages over the software implementation in terms of low power consumption, less area usage and reliability. The advantages of Dual Tree Complex Wavelet Transform (DTCWT) and Principle Component Analysis (PCA) techniques are extracted to improve the robustness and perceptibility. The hardware watermarking solution is more economical, because adding the component only takes up a small dedicated area of silicon. The algorithm is developed and simulated using Matlab, Simulink and system generator. The implementation is carried out using Spartan 6 Diligent Atlys Field Programmable Gate array (FPGA). The architecture uses 256 slice registers, 257 slice Look Up Tables (LUT’s) and 47 I/O pins. It also meets the requirement of high speed architecture with a delay of 1.328ns and an operating frequency of 549.451MHz.

scholarly journals Resolving longitudinal amplitude and phase information of two continuous data streams for high-speed and real-time processing

2009 ◽  
Vol 7 ◽  
pp. 133-137 ◽  
Author(s):  
A. Guntoro ◽  
M. Glesner
Keyword(s):  
Data Streams ◽  
Data Stream ◽  
High Speed ◽  
Hardware Implementation ◽  
Software Implementation ◽  
Phase Detector ◽  
Continuous Data ◽  
Process Data ◽  
Real Time Processing ◽  
High Speed Data

Abstract. Although there is an increase of performance in DSPs, due to its nature of execution a DSP could not perform high-speed data processing on a continuous data stream. In this paper we discuss the hardware implementation of the amplitude and phase detector and the validation block on a FPGA. Contrary to the software implementation which can only process data stream as high as 1.5 MHz, the hardware approach is 225 times faster and introduces much less latency.

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