scholarly journals FPGA Implementation of DTCWT and PCA Based Watermarking Technique

2018 ◽  
Vol 7 (2) ◽  
pp. 82
Author(s):  
M. S. Sudha ◽  
T. C. Thanuja
Keyword(s):  
Wavelet Transform ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Implementation ◽  
Image Watermarking ◽  
Software Implementation ◽  
Low Power Consumption ◽  
Complex Wavelet Transform ◽  
System Generator ◽  
Field Programmable

The hardware implementation of the image watermarking algorithm offers numerous distinct advantages over the software implementation in terms of low power consumption, less area usage and reliability. The advantages of Dual Tree Complex Wavelet Transform (DTCWT) and Principle Component Analysis (PCA) techniques are extracted to improve the robustness and perceptibility. The hardware watermarking solution is more economical, because adding the component only takes up a small dedicated area of silicon. The algorithm is developed and simulated using Matlab, Simulink and system generator. The implementation is carried out using Spartan 6 Diligent Atlys Field Programmable Gate array (FPGA). The architecture uses 256 slice registers, 257 slice Look Up Tables (LUT’s) and 47 I/O pins. It also meets the requirement of high speed architecture with a delay of 1.328ns and an operating frequency of 549.451MHz.

scholarly journals Simple Hardware Implementation of Motion Estimation Algorithms

2019 ◽  
Vol 11 (3) ◽  
Author(s):  
Juan Romero ◽  
Damien Verdier ◽  
Clement Raffaitin ◽  
Luis Miguel Procel ◽  
Lionel Trojman
Keyword(s):  
Optical Flow ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Software Implementation ◽  
Hardware Description Language ◽  
Successful Implementation ◽  
Description Language ◽  
Estimation Algorithms ◽  
Field Programmable ◽  
Hardware Description

We present in the following work a hardware implementation of the two principal optical flow methods. The work is based on the methods developed by Lucas & Kanade, and Horn & Schunck. The implementation is made by using a field programmable gate array and Hardware Description Language. To achieve a successful implementation, the algorithms were optimized. The results show the optical flow as a vector field over one frame, which enable an easy detection of the movement. The results are compared to a software implementation to insure the success of the method. The implementation is a fast implementation capable of quickly overcoming a traditional implementation in software.

scholarly journals Hardware Implementation of MISO on Orthogonal Frequency Division Multiplexing Platform with the Help of Alamouti Algorithm

2017 ◽  
Vol 63 (2) ◽  
pp. 137-143
Author(s):  
Seetaiah Kilaru
Keyword(s):  
Field Programmable Gate Array ◽  
Orthogonal Frequency Division Multiplexing ◽  
Hardware Implementation ◽  
Frequency Division Multiplexing ◽  
Frequency Division ◽  
Test Bed ◽  
System Generator ◽  
Field Programmable ◽  
Simulation Results ◽  
Half Decade

Abstract Many software based OFDM techniques were proposed from last half decade to improve the performance of the system. This paper tried to implement the same with Hardware implementation. We created Hardware based MISO platform with OFDM. We implemented Alamouti algorithm on this test bed. The test bed is implemented with the help of Field Programmable Gate Array (FPGA). The test bed is functionalized with the help of FPGA through Xilinx based system generator for DSP. In this paper we considered the 2×1 MISO implementation with Alamouti algorithm. The simulation results showed that BER and SNR are considerably high for MISO than SISO. The results also proved that proposed OFDM based Alamouti implementation for MISO is excellent in all performance criterions.

scholarly journals Implementation of digital and analog modulation systems using FPGA

2020 ◽  
Vol 18 (1) ◽  
pp. 485
Author(s):  
Raya Kahtan Mohammed ◽  
Hamsa Abdulkareem Abdullah
Keyword(s):  
Signal Processing ◽  
Reconfigurable Computing ◽  
Field Programmable Gate Array ◽  
Development Process ◽  
Hardware Implementation ◽  
Processing System ◽  
Signal Processing System ◽  
System Generator ◽  
Modulation Techniques ◽  
Field Programmable

<p><span>FPGA (Field Programmable Gate Array) based implementations of digital and analog modulation techniques play a vital rule in the design of signal processing system. The performance and flexibility provided by reconfigurable computing speeds up the development process in signal processing implementations using FPGA. Different methods for digital and analog modulation are designed in this paper by usinSg System Generator tools &amp; Vivado. Then all designed systems are implemented successfully in an FPGA hardware via the NEXYS 4 DDR with ARTIX 7 XC7A100T. A comparison between five types of digital modulation techniques is discussed in terms of resources utilization in FPGA hardware. And also, the implementation of analog modulations in FPGA is contributed in this work. The hardware implementation shows that the number of slice LUTs in ASK modulation is 0.07% while in FSK modulation is 0.13% of the total number of slice LUTs. And also, the number of bounded IO that used for PSK modulation is 4.8% while in PM modulation is 61.4% of the total number bounded IO.</span></p>

Based on FPGA Intelligent Physiological Parameters Acquisition

2013 ◽  
Vol 344 ◽  
pp. 107-110
Author(s):  
Shun Ren Hu ◽  
Ya Chen Gan ◽  
Ming Bao ◽  
Jing Wei Wang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Physiological Parameters ◽  
Sensor Data ◽  
Low Power Consumption ◽  
Physiological Signal ◽  
Pulse Sensor ◽  
Monitoring Applications ◽  
Field Programmable ◽  
Design Ideas

For the physiological signal monitoring applications, as a micro-controller based on field programmable gate array (FPGA) physiological parameters intelligent acquisition system is given, which has the advantages of low cost, high speed, low power consumption. FPGA is responsible for the completion of pulse sensor, the temperature sensor, acceleration sensor data acquisition and serial output and so on. Focuses on the design ideas and architecture of the various subsystems of the whole system, gives the internal FPGA circuit diagram of the entire system. The whole system is easy to implement and has a very good promotional value.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

2018 ◽  
Vol 7 (4) ◽  
pp. 2569
Author(s):  
Priyanka Chauhan ◽  
Dippal Israni ◽  
Karan Jasani ◽  
Ashwin Makwana
Keyword(s):  
Power Consumption ◽  
Data Acquisition ◽  
Resource Utilization ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
State Of The Art ◽  
Data Rate ◽  
Field Programmable ◽  
Sensor Signals ◽  
Acquisition Technique

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.  

scholarly journals A SIMULATION MODEL FOR ROBOT’S SLIP DISPLACEMENT SENSORS

2016 ◽  
pp. 224-236 ◽  
Author(s):  
Yuriy Kondratenko ◽  
Oleksandr Gerasin ◽  
Andriy Topalov
Keyword(s):  
Simulation Model ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Displacement Sensor ◽  
Clamping Force ◽  
Sensing System ◽  
Displacement Sensors ◽  
Field Programmable ◽  
Slip Displacement ◽  
Corrosive Environments

This paper deals with a simulation model of slip displacement sensors for the object slip signals’ registration in the adaptive robot’s gripper. The study presents the analysis of different methods for slip displacement signals detection, as well as authors’ solutions. Special attention is paid to the investigations of the developed sensor with the resistive registration element in rod type structure of sensitive elements, which is able to operate in harsh and corrosive environments. A sensing system for the object slip signals’ registration in the adaptive robot’s gripper with a clamping force correction is developed for proposed slip displacement sensor with multi-component resistive registration elements. The hardware implementation of the sensing system for slip signals’ registration and obtained results are considered in details. The simulation model of the proposed slip displacement sensor based on polytypic conductive rubber is modeled by Proteus software. The intelligent approaches with the use of a field programmable gate array (FPGA) and VHDL-model to the sensing system designing allow to define the slippage direction in slip displacement sensor based on resistive registration elements. Thus, this expands the functionality of the developed sensor.

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