scholarly journals CMOS Implementation of Threshold Gates with Hysteresis

Author(s):  
Farhad A. Parsan ◽  
Scott C. Smith
Keyword(s):  
Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 155
Author(s):  
Luca Gnoli ◽  
Fabrizio Riente ◽  
Marco Vacca ◽  
Massimo Ruo Roch ◽  
Mariagrazia Graziano

In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searching for the maximum/minimum number. The circuit has been designed and validated using physical simulations for the memory array together with digital design tools for the control logic. The results highlight the small area of the proposed architecture and its good energy efficiency compared with a reference CMOS implementation.


2005 ◽  
Vol 152 (6) ◽  
pp. 579 ◽  
Author(s):  
T. Morimoto ◽  
Y. Harada ◽  
T. Koide ◽  
H.J. Mattausch

Adder Is Basic Unit For Any Digital System, Dsp And Microprocessor. The Main Issue In Design High Speed Full Adder Cell With The Low Power Dissipation. As We Know Cmos Technology Used For Vlsi Designing Cmos Has Many Drawbacks As High Power Short Channel Effect Etc. Then Cntfet (Carbon Nanotube Field Effect Transistor) Has Been Developed Which Has Same Structure As Cmos. The Difference Between Structure Of Cmos And Cntfet Is Their Channel. In Cntfet Channel Is Replaced By Carbon Nanotube. In This Paper We Compare Full Adder Circuit Using Cntfet With Gdi Technique And Cmos Implementation Of Adder Which Gdi Technique. Gdi Technique Is Used For Speed And Power Optimization In Digital Circuit. This Can Also Reduce The Count Of Transistor Which Affects The Size Of Device.


Author(s):  
Masanori Hashimoto ◽  
Xu Bai ◽  
Naoki Banno ◽  
Munehiro Tada ◽  
Toshitsugu Sakamoto ◽  
...  
Keyword(s):  

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