scholarly journals Parallel Transistor-Level Circuit Simulation

2011 ◽  
pp. 1-21 ◽  
Author(s):  
Eric R. Keiter ◽  
Heidi K. Thornquist ◽  
Robert J. Hoekstra ◽  
Thomas V. Russo ◽  
Richard L. Schiek ◽  
...  
Keyword(s):  
Circuit Simulation

Nonlinear Circuit Simulation and Modeling

2018 ◽  
Author(s):  
José Carlos Pedro ◽  
David E. Root ◽  
Jianjun Xu ◽  
Luís Cótimos Nunes
Keyword(s):  
Circuit Simulation ◽  
Simulation And Modeling ◽  
Nonlinear Circuit

Editorial: Techniques for nonlinear circuit simulation

1994 ◽  
Vol 141 (4) ◽  
pp. 241
Author(s):  
P.J. Mole ◽  
G.M.S. Rokos
Keyword(s):  
Circuit Simulation ◽  
Nonlinear Circuit

Failure Analysis Due to Slightly Unetched Hard Mask Using Nano Probe

2013 ◽  
Author(s):  
Jong Hak Lee ◽  
Jong Eun Kim ◽  
Chang Su Park ◽  
Nam Il Kim ◽  
Jang Won Moon ◽  
...  
Keyword(s):  
Leakage Current ◽  
Circuit Simulation ◽  
The State ◽  
Physical Analysis ◽  
Cross Sectional ◽  
Hard Mask ◽  
Current Flows ◽  
Voltage Contrast ◽  
The One ◽  
Zero Voltage

Abstract In this work, a slightly unetched gate hard mask failure was analyzed by nano probing. Although unetched hard mask failures are commonly detected from the cross sectional view with FIB or FIB-TEM and planar view with the voltage contrast, in this case of the very slightly unetched hard mask, it was difficult to find the defects within the failed area by physical analysis methods. FIB is useful due to its function of milling and checking from the one region to another region within the suspected area, but the defect, located under contact was very tiny. So, it could not be detected in the tilted-view of the FIB. However, the state of the failure could be understood from the electrical analysis using a nano probe due to its ability to probe contact nodes across the fail area. Among the transistors in the fail area, one transistor’s characteristics showed higher leakage current and lower ON current than expected. After physical analysis, slightly remained hard mask was detected by TEM. Chemical processing was followed to determine the gate electrode (WSi2) connection to tungsten contact. It was also proven that when gate is floated, more leakage current flows compared to the state that the zero voltage is applied to the gate. This was not verified by circuit simulation due to the floating nodes.

CIRCUIT SIMULATION OF SINGLE FAILURES OF MEMORY MODULES OF ON–BOARD ELECTRONICS

2020 ◽  
Vol 3 (331) ◽  
pp. 118-126
Author(s):  
Grichshenko V.F., ◽  
◽  
Mukushev A.A., ◽  
◽  
Keyword(s):  
Circuit Simulation ◽  
Memory Modules
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