Dynamic Modelling of Mechanisms. Qualifying of Three Integration Schemes

Author(s):  
Michel Abadie ◽  
Claude Bohatier
2003 ◽  
Vol 766 ◽  
Author(s):  
Kenneth Foster ◽  
Joost Waeterloos ◽  
Don Frye ◽  
Steve Froelicher ◽  
Mike Mills

AbstractThe electronics industry, in a continual drive for improved integrated device performance, is seeking increasingly lower dielectric constants (k) of the insulators that are used as interlayer dielectric (ILD) for advanced logic interconnects. As the industry continually seeks a stepwise reduction of the “effective” dielectric constant (keff), simple extendibility, leads to the consideration of the highest performance possible, namely air bridge technology. In this paper we will discuss requirements, integration schemes and properties for a novel class of materials that has been developed as part of an advanced technology probe into air bridge architecture. We will compare and contrast these potential technology offerings with other existing dense and porous ILD integration options, and show that the choice is neither trivial nor obvious.


2010 ◽  
Vol 3 (1) ◽  
pp. 49-56 ◽  
Author(s):  
Navid Mostoufi ◽  
Ali Faridkhou ◽  
Rahmat Sotudeh Gharebagh ◽  
Hamid Reza Norouzi

2003 ◽  
Vol 1 (01) ◽  
pp. 441-445
Author(s):  
I. Zubia ◽  
◽  
S.K. Salman ◽  
X. Ostolaza ◽  
G. Tapia ◽  
...  

2018 ◽  
Vol 11 (48) ◽  
pp. 156-160
Author(s):  
Razumov E.A. ◽  
◽  
Wenger V.G. ◽  
Zelyaeva E.A. ◽  
Petrov V.I. ◽  
...  

2005 ◽  
Author(s):  
Marzena M. Olewczynska ◽  
Jurgen Grotsch ◽  
Jamal Al Jundi ◽  
Shankar Rao

2006 ◽  
Vol 5 (4) ◽  
pp. 705-716 ◽  
Author(s):  
Li Shi ◽  
Catherine Cadet ◽  
Pierre-Xavier Thivel ◽  
Francoise Delpech

Author(s):  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Fred Towler ◽  
Stephen Wu ◽  
Zhigang Song ◽  
...  

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.


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