Effects of cobalt deposition and pretreatment process on electrical properties of products

The preferable conditions for formation of high quality CoSi2 films and effect of process parameters on properties of products were investigated. The pretreatment should not only remove the natural oxide layer completely, but also could not damage Si substrate. The good static random access memory (SRAM) proportion of products is high when pretreatment thickness is 20 Å, reached 96.5%. The radio frequency (RF) bias power process parameter should also take an optimal value. When RF bias power is 150 W, the good SRAM proportion of products is greater than 98%. The 100 Å Co can just completely react with Si substrate after twice annealing (500℃ 30s and 750℃ 30s), and if it exceeds 100 Å, Co will be residual. Decreasing Co thickness leads to contact resistance (RC) increase whatever in N-well or P-well. The overall standby current (Isb) of product is least when Co thickness is 80 Å. Finally, the products achieved good electrical properties when Co thickness is 80 Å, pretreatment thickness is 20 Å and RF bias power is 150 W.

One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

<span>This article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions.</span>