Challenges and Benefits of Product-Like SRAM in Technology Development

2011 ◽  
Author(s):  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Fred Towler ◽  
Stephen Wu ◽  
Zhigang Song ◽  
...  
Keyword(s):  
Technology Development ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Development Phase ◽  
High Complexity ◽  
Access Memory ◽  
Integration Schemes ◽  
Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

AS8‐static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

2017 ◽  
Vol 11 (1) ◽  
pp. 89-94 ◽  
Author(s):  
Ihsen Alouani ◽  
Wael M. Elsharkasy ◽  
Ahmed M. Eltawil ◽  
Fadi J. Kurdahi ◽  
Smail Niar
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Soft Error ◽  
Static Random Access Memory ◽  
Access Memory

scholarly journals Pitfall of the Strongest Cells in Static Random Access Memory Physical Unclonable Functions

Sensors ◽  
2018 ◽  
Vol 18 (6) ◽  
pp. 1776 ◽  
Author(s):  
Mingyang Gong ◽  
Hailong Liu ◽  
Run Min ◽  
Zhenglin Liu
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Physical Unclonable Functions

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

Two‐Dimensional Materials‐Based Static Random‐Access Memory

2021 ◽  
pp. 2107894
Author(s):  
Chang‐Ju Liu ◽  
Yi Wan ◽  
Lain‐Jong Li ◽  
Chih‐Pin Lin ◽  
Tuo‐Hung Hou ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Two Dimensional ◽  
Access Memory ◽  
Two Dimensional Materials
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