Switched Capacitor Circuit Realization of Sigma-Delta ADC for Temperature Sensor

Author(s):  
Abhishek Pandey ◽  
Mohd. Javed Khan ◽  
Deepak Prasad ◽  
Vijay Nath ◽  
S. S. Solanki ◽  
...  
Micromachines ◽  
2018 ◽  
Vol 9 (8) ◽  
pp. 372 ◽  
Author(s):  
Risheng Lv ◽  
Weiping Chen ◽  
Xiaowei Liu

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.


Author(s):  
Deepak Prasad ◽  
Vijay Nath

In the current paper, an accurate with low power consumed sigma delta (ΣΔ) analog to digital converter has been designed for the aerospace applications. The sigma delta ADC has been designed in such a way that it works fine with consumption of low power and high accuracy in the system on chip (SoC) temperature sensor where the analog output from the temperature sensor unit will be the fed to the analog to digital converter. To check the robustness, different parameters with variation has been analyzed. The high gain operational amplifier plays a vital role in the circuits design. Hence, a 30 MHz operational amplifier has also been proposed whose unity gain bandwidth (UGB) has been observed of about 30 MHz, 51.1dB dc gain and slew rate (SR) of about 27.9 V/ μsec. For the proper operation of the circuit, a power supply of +1.3V to -1.3V is used. The proposed sigma delta ADC modulator is showing better results over previously designed modulator in terms of power consumption, error and performance. The design and simulation have been tested with the help of cadence analog design environment with UMC 90nm CMOS process technology.


2019 ◽  
Vol 16 (4) ◽  
pp. 20181025-20181025
Author(s):  
Xianliang Chen ◽  
Linxiang Li ◽  
Xi Tan ◽  
Na Yan ◽  
Junyu Wang ◽  
...  

2020 ◽  
Vol 63 (11) ◽  
pp. 586-595
Author(s):  
Alexander Korotkov ◽  
Dmitry Morozov ◽  
Mikhail Pilipko ◽  
Mikhail Yenuchenko

2007 ◽  
Vol 42 (11) ◽  
pp. 2357-2368 ◽  
Author(s):  
Teng-Hung Chang ◽  
Lan-Rong Dung ◽  
Jwin-Yen Guo ◽  
Kai-Jiun Yang
Keyword(s):  

Author(s):  
Nan Qi ◽  
Zheng Song ◽  
Zehong Zhang ◽  
Yang Xu ◽  
Baoyong Chi ◽  
...  

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