scholarly journals Low Power and High Speed 4-Bit Flash Analog to Digital Converter Using Dynamic Latch Comparator Technique

2015 ◽  
Vol 4 (8) ◽  
pp. 6881-6886
Author(s):  
K.Sarath Chandra, V.Gowtam Raj Kumar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital

scholarly journals A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

2017 ◽  
Vol 2017 ◽  
pp. 1-15 ◽  
Author(s):  
Mostafa Chakir ◽  
Hicham Akhamal ◽  
Hassan Qjidaa
Keyword(s):  
Low Power ◽  
Input Signal ◽  
Small Area ◽  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Active Pixel Sensor ◽  
Analog To Digital ◽  
Active Pixel ◽  
5 Ghz

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450059 ◽  
Author(s):  
MAO YE ◽  
BIN WU ◽  
YONGXU ZHU ◽  
YUMEI ZHOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Dynamic Range ◽  
Cmos Process ◽  
Area Network ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Silicon Area ◽  
Analog To Digital

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

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