Optimization of 2D Ge-Pocket Asymmetric Dual-Gate Tunnel FETs

2021 ◽  
pp. 273-279
Author(s):  
Neeraj Kumar Niranjan ◽  
Sagarika Choudhary ◽  
Madhuchanda Choudhary ◽  
Krishna Lal Baishanb
Keyword(s):  
2016 ◽  
Vol 56 (1) ◽  
pp. 014301
Author(s):  
Hui Fang Xu ◽  
Yue Hua Dai ◽  
Bang Gui Guan ◽  
Yong Feng Zhang

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset

Author(s):  
Cheng-Piao Lin ◽  
Chin-Hsin Tang ◽  
Cheng-Hsu Wu ◽  
Cheng-Chun Ting

Abstract This paper analyzes several SRAM failures using nano-probing technique. Three SRAM single bit failures with different kinds of Gox breakdown defects analyzed are gross function single bit failure, data retention single bit failure, and special data retention single bit failure. The electrical characteristics of discrete 6T-SRAM cells with soft breakdown are discussed and correlated to evidences obtained from physical analysis. The paper also verifies many previously published simulation data. It utilizes a 6T-SRAM vehicle consisting of a large number of SRAM cells fabricated by deep sub-micron, dual gate, and copper metallization processes. The data obtained from this paper indicates that Gox breakdown location within NMOS pull-down device has larger a impact on SRAM stability than magnitude of gate leakage current, which agrees with previously published simulation data.


1971 ◽  
Vol 7 (22) ◽  
pp. 661 ◽  
Author(s):  
J.A. Turner ◽  
A.J. Waller ◽  
E. Kelly ◽  
D. Parker

2005 ◽  
Author(s):  
D.C.H. Yu ◽  
K.H. Lee ◽  
A. Kornblit ◽  
C.C. Fu ◽  
R.H. Yan ◽  
...  
Keyword(s):  

Author(s):  
Chunsheng Chen ◽  
Yongli He ◽  
Li Zhu ◽  
Ying Zhu ◽  
Yi Shi ◽  
...  

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