Analysis and Implementation of Less Delay and Low Area DT Multiplier

2022 ◽  
pp. 25-32
Author(s):  
J. N. Swaminathan ◽  
K. Ambujam ◽  
V. Madhava Reddy ◽  
P. Mahesh ◽  
Ch. Harika ◽  
...  
Keyword(s):  
Low Area

A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller

2021 ◽  
pp. 1-11
Author(s):  
Peng Yin ◽  
Zhou Shu ◽  
Yingjun Xia ◽  
Tianmei Shen ◽  
Xiao Guan ◽  
...  
Keyword(s):  
Low Power ◽  
Word Alignment ◽  
Low Area

Low-area and accurate inner product and digital filters based on stochastic computing

2021 ◽  
Vol 183 ◽  
pp. 108040
Author(s):  
Hamdan Abdellatef ◽  
Mohamed Khalil-Hani ◽  
Nasir Shaikh-Husin ◽  
Sayed Omid Ayat
Keyword(s):  
Digital Filters ◽  
Inner Product ◽  
Low Area ◽  
Stochastic Computing

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

2021 ◽  
Author(s):  
Chaudhry Indra Kumar
Keyword(s):  
Energy Transfer ◽  
Energy Efficient ◽  
Linear Energy Transfer ◽  
Mixed Mode ◽  
Biomedical Applications ◽  
Soft Errors ◽  
Cmos Technology ◽  
Radiation Hardness ◽  
Memory Element ◽  
Low Area

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.

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