An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

Journal of Circuits System and Computers ◽

10.1142/s0218126622501250 ◽

2021 ◽

Author(s):

Chaudhry Indra Kumar

Keyword(s):

Energy Transfer ◽

Energy Efficient ◽

Linear Energy Transfer ◽

Mixed Mode ◽

Biomedical Applications ◽

Soft Errors ◽

Cmos Technology ◽

Radiation Hardness ◽

Memory Element ◽

Low Area

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.

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Band gap engineered resistor for mitigating linear energy transfer sensitivities in scaled submiron CMOS technology SRAM cells

Solid-State Electronics ◽

10.1016/j.sse.2008.06.005 ◽

2008 ◽

Vol 52 (10) ◽

pp. 1555-1562

Author(s):

Esau Kanyogoro ◽

Martin Peckerar ◽

Harold Hughes ◽

Mike Liu

Keyword(s):

Energy Transfer ◽

Band Gap ◽

Linear Energy Transfer ◽

Cmos Technology

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Linear energy transfer (biology)

AccessScience ◽

10.1036/1097-8542.384100 ◽

2015 ◽

Keyword(s):

Energy Transfer ◽

Linear Energy Transfer

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Unresectable Chondrosarcomas Treated With Carbon Ion Radiotherapy: Relationship Between Dose-averaged Linear Energy Transfer and Local Recurrence

Anticancer Research ◽

10.21873/anticanres.14664 ◽

2020 ◽

Vol 40 (11) ◽

pp. 6429-6435

Author(s):

SHINNOSUKE MATSUMOTO ◽

SUNG HYUN LEE ◽

REIKO IMAI ◽

TAKU INANIWA ◽

NARUHIRO MATSUFUJI ◽

...

Keyword(s):

Energy Transfer ◽

Local Recurrence ◽

Linear Energy Transfer ◽

Carbon Ion Radiotherapy ◽

Carbon Ion

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CMOS-MEMS Based Current Mirror MOSFET Embedded Pressure Sensor for Healthcare and Biomedical Applications

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.647.315 ◽

2013 ◽

Vol 647 ◽

pp. 315-320 ◽

Cited By ~ 6

Author(s):

Pradeep Kumar Rathore ◽

Brishbhan Singh Panwar

Keyword(s):

Pressure Sensor ◽

Biomedical Applications ◽

Circuit Simulation ◽

Applied Pressure ◽

Pressure Sensors ◽

Cmos Technology ◽

Current Mirror ◽

Sensing Element ◽

Pressure Sensing ◽

Cmos Mems

This paper reports on the design and optimization of current mirror MOSFET embedded pressure sensor. A current mirror circuit with an output current of 1 mA integrated with a pressure sensing n-channel MOSFET has been designed using standard 5 µm CMOS technology. The channel region of the pressure sensing MOSFET forms the flexible diaphragm as well as the strain sensing element. The piezoresistive effect in MOSFET has been exploited for the calculation of strain induced carrier mobility variation. The output transistor of the current mirror forms the active pressure sensing MOSFET which produces a change in its drain current as a result of altered channel mobility under externally applied pressure. COMSOL Multiphysics is utilized for the simulation of pressure sensing structure and Tspice is employed to evaluate the characteristics of the current mirror pressure sensing circuit. Simulation results show that the pressure sensor has a sensitivity of 10.01 mV/MPa. The sensing structure has been optimized through simulation for enhancing the sensor sensitivity to 276.65 mV/MPa. These CMOS-MEMS based pressure sensors integrated with signal processing circuitry on the same chip can be used for healthcare and biomedical applications.

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A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

EURASIP Journal on Advances in Signal Processing ◽

10.1186/s13634-020-00708-0 ◽

2020 ◽

Vol 2020 (1) ◽

Author(s):

Yuan-Ho Chen ◽

Chieh-Yang Liu

Keyword(s):

Video Coding ◽

Large Scale ◽

High Efficiency ◽

Vlsi Design ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Time Sharing ◽

High Efficiency Video Coding ◽

Low Area ◽

Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

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