A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits

2017 ◽  
Vol 37 (4) ◽  
pp. 1692-1703 ◽  
Author(s):  
Chua-Chin Wang ◽  
Zong-You Hou ◽  
Chih-Lin Chen ◽  
Doron Shmilovitz
Keyword(s):  
Low Power ◽  
Clock And Data Recovery ◽  
Data Recovery

scholarly journals Design and Implementation of Low Power Delay Locked Loop using Multiplexer Based Phase Frequency Detector

2020 ◽  
Vol 9 (5) ◽  
pp. 951-955
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Clock Recovery ◽  
Clock Frequency ◽  
Phase Frequency Detector ◽  
Delay Locked Loop ◽  
Design And Implementation ◽  
Frequency Detector

This paper proposes design and implementation of low power Delay Locked Loop Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum locking time. Clock and data recovery systems are employed to derive the clocking information to correctly decode the transmitted data at the receiver. Delay Locked Loop is one of the most important clock recovery systems. The DLL architecture is designed using Cadence Virtuoso 180nm Technology with 1.8V power supply. The proposed DLL with Multiplexer based phase frequency detector shows significant reduction in power dissipation by 10% compared to DLL designed using D-FF based PFD and achieves locking state within 10 clock cycles with minimum jitter of 4.84326ps, measured within clock frequency range of 100-250MHz.

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