Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

A High-Performance Full Adder Circuit Based on a Novel 7-T XOR-XNOR Cell

2013 ◽  
Vol 321-324 ◽  
pp. 361-366
Author(s):  
Yan Yu Ding ◽  
De Ming Wang ◽  
Qing Qing Huang ◽  
Hong Zhou Tan
Keyword(s):  
Power Dissipation ◽  
High Performance ◽  
Critical Path ◽  
Full Adder ◽  
Path Delay ◽  
Feedback Path ◽  
Voltage Loss ◽  
Transmission Gates ◽  
Voltage Swing ◽  
Power Delay Product

A high performance full adder circuit with full voltage-swing based on a novel 7-transistor xor-xnor cell is proposed in this paper. In our design, we exploit a novel 7-transistor xor-xnor circuit with a signal level restorer in a feedback path to settle the threshold voltage loss problem. Then we present a new high-performance 1-bit full adder based on the designed xor-xnor cell, pass-transistors and transmission gates. The simulation results prove that, compared with other designs in literature, the proposed full adder shows its superiority for less power dissipation, lower critical path delay and smaller power-delay product, and still provides full voltage swing in all nodes of the circuit.

scholarly journals Full Adder for Low Power Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 2682-2687
Keyword(s):  
Low Power ◽  
Processing System ◽  
Full Adder ◽  
Cmos Technology ◽  
Fundamental Operation ◽  
Dynamic Power ◽  
Power Delay Product ◽  
Electronic Processing

In an electronic processing system, addition of binary numbers is a fundamental operation. A one bit low power hybrid FA(full adder) is shown in showing performance improvisation by analysis and comparing with other conventional adders. 1 bit low power hybrid full adder is considered as a good way for enhancing the speed of the circuit in comparison with other conventional circuits of full adders. In that analysis paper, one bit low power hybrid FA(full adder) is implemented by EDA tool and the simulation is analysis by using generic 90nm CMOS technology at 5 volts and comparison is done at various voltages with other conventional full adders. For comparing 1 bit low power hybrid full adder with other conventional adders at various parameters such as static and dynamic power usage, delay & pdp (power delay product) are taken into consideration to show that 1 bit low power hybrid full adder is most suitable for various low power applications.

Design of Low Power CMOS Comparator using 180nm Technology for ADC Application

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 11-13
Author(s):  
Truptimayee Behera ◽  
Ritisnigdha Das
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Clock Frequency ◽  
Nmos Transistor ◽  
Body Effect ◽  
Low Power Dissipation ◽  
Low Power Cmos

In our design of CMOS comparator with high performance using GPDK 180nm technology we optimize these parameters. We analyse the transient response of the schematic design and the gain is calculated in AC analysis and also we measure the power dissipation. The circuit is built by using PMOS and NMOS transistor with a body effect. A plot of phase and gain also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 2V is measured using Cadence virtuoso. Simulation results are presented and it shows that this design can work under high speed clock frequency 200MHz. The design has low power dissipation.

scholarly journals An Area Efficient Wallace Tree Multiplier using Modified Full Adder

2020 ◽  
Vol 8 (6) ◽  
pp. 3383-3386
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Nand Gate ◽  
Silicon Area ◽  
Wallace Tree ◽  
Multiplication Process ◽  
Wallace Tree Multiplier ◽  
Area Efficient

Multipliers play a significant task in digital signal processing applications and application-specific integrated circuits. Wallace tree multipliers provide a high-speed multiplication process with an area-efficient strategy. It is realized in hardware using full adders and half adders. The optimization of adders can further improve the performance of multipliers. Wallace tree multiplier with modified full adder using NAND gate is proposed to achieve reduced silicon area, high speed and low power consumption. The conventional full adder implemented by XOR, AND, OR gates is replaced by the modified full adder realized using NAND gate. The proposed Wallace tree multiplier includes 544 transistors, while the conventional Wallace tree multiplier has 584 transistors for 4-bit multiplication.

scholarly journals Ultra high speed full adder for biomedical applications

2021 ◽  
Vol 10 (1) ◽  
pp. 25
Author(s):  
Basavoju Harish ◽  
M. S. S. Rukmini
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Medical Engineering ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Devices ◽  
Ripple Carry Adder ◽  
Power Delay Product

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder

2021 ◽  
Vol 14 ◽  
Author(s):  
Priyanka Tyagi ◽  
Sanjay Kumar Singh ◽  
Piyush Dua
Keyword(s):  
High Speed ◽  
Full Adder ◽  
Additional Advantage ◽  
Power Efficient ◽  
Digital World ◽  
Diffusion Technique ◽  
Low Power Dissipation ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Full Swing

Background: Full adder is the key element of the digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with new Gate diffusion technique has been implemented in this work. There is the comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultralow power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit moreover it also reduces number of transistors required. This technique has been used with CNTFET to upgrade full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The Finfet design also shows the better performance with GDI. But GDI enhance CNTFET based design power consumption about 32% from the FinFET. Conclusions: CNTFET observed the better response due to good current conductivity as compare to the FinFET. This work has been implemented and simulated on the 32nm node technology.

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