Enhanced analog performance of doping-less dual material and gate stacked architecture of junctionless transistor with high-k spacer

Applied Physics A ◽

10.1007/s00339-016-9904-2 ◽

2016 ◽

Vol 122 (4) ◽

Author(s):

S. Intekhab Amin ◽

R. K. Sarin

Keyword(s):

High K ◽

Analog Performance ◽

Junctionless Transistor ◽

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A Dual-Material Gate Junctionless Transistor With High-$k$ Spacer for Enhanced Analog Performance

IEEE Transactions on Electron Devices ◽

10.1109/ted.2013.2292852 ◽

2014 ◽

Vol 61 (1) ◽

pp. 123-128 ◽

Author(s):

Ratul K. Baruah ◽

Roy P. Paily

Keyword(s):

High K ◽

Analog Performance ◽

Junctionless Transistor ◽

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Charge-plasma based dual-material and gate-stacked architecture of junctionless transistor for enhanced analog performance

Superlattices and Microstructures ◽

10.1016/j.spmi.2015.10.017 ◽

2015 ◽

Vol 88 ◽

pp. 582-590 ◽

Author(s):

S. Intekhab Amin ◽

R.K. Sarin

Keyword(s):

Charge Plasma ◽

Analog Performance ◽

Junctionless Transistor ◽

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A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_15 ◽

2013 ◽

pp. 118-127 ◽

Author(s):

Ratul Kumar Baruah ◽

Roy P. Paily

Keyword(s):

Double Layer ◽

Analog Performance ◽

Junctionless Transistor ◽

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Comparison study of Dual Material Gate Silicon on Insulator junctionless Transistor and with Junction Transistor for Analog Performance

International Journal of Materials Mechanics and Manufacturing ◽

10.18178/ijmmm.2019.7.3.448 ◽

2019 ◽

Vol 7 (3) ◽

pp. 144-149

Author(s):

S. C. Wagaj ◽

◽

S. C. Patil

Keyword(s):

Silicon On Insulator ◽

Comparison Study ◽

Analog Performance ◽

Junctionless Transistor ◽

Junction Transistor ◽

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The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

Journal of Semiconductors ◽

10.1088/1674-4926/36/9/094001 ◽

2015 ◽

Vol 36 (9) ◽

pp. 094001 ◽

Author(s):

S. Intekhab Amin ◽

R. K. Sarin

Keyword(s):

Double Gate ◽

Analog Performance ◽

Junctionless Transistor ◽

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High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime

IEEE Transactions on Electron Devices ◽

10.1109/ted.2018.2873717 ◽

2018 ◽

Vol 65 (12) ◽

pp. 5282-5288

Author(s):

Yumei Yang ◽

Haijun Lou ◽

Xinnan Lin

Keyword(s):

Ballistic Regime ◽

High K ◽

Junctionless Transistor

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2-D analytical modeling of dual material gate fully depleted SOI MOSFET with high-k dielectric

Acta Physica Sinica ◽

10.7498/aps.57.3807 ◽

2008 ◽

Vol 57 (6) ◽

pp. 3807

Author(s):

Luan Su-Zhen ◽

Liu Hong-Xia ◽

Jia Ren-Xu ◽

Cai Nai-Qiong

Keyword(s):

Analytical Modeling ◽

Fully Depleted ◽

High K ◽

High K Dielectric ◽

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Performance Scrutiny of Source and Drain-Engineered Dual-Material Double-Gate (DMDG) SOI MOSFET with Various High-K

Advances in Intelligent Systems and Computing - Intelligent Engineering Informatics ◽

10.1007/978-981-10-7566-7_53 ◽

2018 ◽

pp. 533-539

Author(s):

Himanshu Yadav ◽

R. K. Chauhan

Keyword(s):

Double Gate ◽

High K ◽

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Surface potential based Analytical Modeling of Graded Channel Strained High-k Gate stack Dual-Material Double Gate MOSFET

2019 Devices for Integrated Circuit (DevIC) ◽

10.1109/devic.2019.8783284 ◽

2019 ◽

Author(s):

Pritha Banerjee ◽

Priyanka Saha ◽

Dinesh Kumar Dash ◽

Subir Kumar Sarkar

Keyword(s):

Surface Potential ◽

Analytical Modeling ◽

Double Gate ◽

High K ◽

Double Gate Mosfet ◽

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Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals

Silicon ◽

10.1007/s12633-020-00669-x ◽

2020 ◽

Author(s):

Achinta Baidya ◽

T. R. Lenka ◽

S. Baishya

Keyword(s):

Double Gate ◽

High K ◽

Distortion Analysis ◽

Junctionless Transistor

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