High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime

IEEE Transactions on Electron Devices ◽

10.1109/ted.2018.2873717 ◽

2018 ◽

Vol 65 (12) ◽

pp. 5282-5288

Author(s):

Yumei Yang ◽

Haijun Lou ◽

Xinnan Lin

Keyword(s):

Ballistic Regime ◽

High K ◽

Junctionless Transistor

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Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals

Silicon ◽

10.1007/s12633-020-00669-x ◽

2020 ◽

Author(s):

Achinta Baidya ◽

T. R. Lenka ◽

S. Baishya

Keyword(s):

Double Gate ◽

High K ◽

Distortion Analysis ◽

Junctionless Transistor

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Impact of High-k spacer and Negative Capacitance on Double Gate Junctionless Transistor for Improved Short Channel Immunity and Reliability

2018 4th International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2018.8605167 ◽

2018 ◽

Author(s):

Hema Mehta ◽

Harsupreet Kaur

Keyword(s):

Negative Capacitance ◽

Double Gate ◽

Short Channel ◽

High K ◽

Junctionless Transistor

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A Dual-Material Gate Junctionless Transistor With High-$k$ Spacer for Enhanced Analog Performance

IEEE Transactions on Electron Devices ◽

10.1109/ted.2013.2292852 ◽

2014 ◽

Vol 61 (1) ◽

pp. 123-128 ◽

Author(s):

Ratul K. Baruah ◽

Roy P. Paily

Keyword(s):

High K ◽

Analog Performance ◽

Junctionless Transistor ◽

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Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

Superlattices and Microstructures ◽

10.1016/j.spmi.2017.03.012 ◽

2017 ◽

Vol 104 ◽

pp. 470-476 ◽

Author(s):

J. Charles Pravin ◽

D. Nirmal ◽

P. Prajoon ◽

N. Mohan Kumar ◽

J. Ajayan

Keyword(s):

Memory Circuit ◽

High K ◽

Junctionless Transistor ◽

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Impact of high-k spacer on device performance of a junctionless transistor

Journal of Computational Electronics ◽

10.1007/s10825-012-0428-5 ◽

2012 ◽

Vol 12 (1) ◽

pp. 14-19 ◽

Author(s):

Ratul Kumar Baruah ◽

Roy P. Paily

Keyword(s):

Device Performance ◽

High K ◽

Junctionless Transistor

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Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor

Materials Science in Semiconductor Processing ◽

10.1016/j.mssp.2017.08.031 ◽

2017 ◽

Vol 71 ◽

pp. 413-420 ◽

Author(s):

Achinta Baidya ◽

Srimanta Baishya ◽

Trupti Ranjan Lenka

Keyword(s):

Double Gate ◽

High K ◽

Junctionless Transistor

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Enhanced analog performance of doping-less dual material and gate stacked architecture of junctionless transistor with high-k spacer

Applied Physics A ◽

10.1007/s00339-016-9904-2 ◽

2016 ◽

Vol 122 (4) ◽

Author(s):

S. Intekhab Amin ◽

R. K. Sarin

Keyword(s):

High K ◽

Analog Performance ◽

Junctionless Transistor ◽

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Impact of high k spacer on RF stability performance of double gate junctionless transistor

International Journal of Numerical Modelling Electronic Networks Devices and Fields ◽

10.1002/jnm.2481 ◽

2018 ◽

Vol 32 (1) ◽

pp. e2481 ◽

Author(s):

Veerati Raju ◽

K. Sivasankaran

Keyword(s):

Double Gate ◽

Stability Performance ◽

High K ◽

Junctionless Transistor

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Impact of temperature on the performance of sub-35nm symmetric Double Gate Junctionless Transistor based inverter using High-K gate dielectric, a TCAD simulation study

2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES) ◽

10.1109/icpeices.2016.7853735 ◽

2016 ◽

Author(s):

Uttam Ch. Boro ◽

Nipanka Bora ◽

Pankaj Appun Pegu ◽

Rupaban Subadar

Keyword(s):

Simulation Study ◽

Gate Dielectric ◽

Double Gate ◽

High K ◽

Junctionless Transistor ◽

Tcad Simulation ◽

High K Gate Dielectric

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Electrical characterization of n-type cylindrical gate all around nanowire junctionless transistor with SiO2 and high-k dielectrics

2020 IEEE International Conference on Semiconductor Electronics (ICSE) ◽

10.1109/icse49846.2020.9166886 ◽

2020 ◽

Author(s):

Nurul Ezaila Alias ◽

Mohammed Adamu Sule ◽

Michael Loong Peng Tan ◽

Afiq Hamzah ◽

Kabiru Adamu Saidu ◽

...

Keyword(s):

Electrical Characterization ◽

High K ◽

Junctionless Transistor

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