A new hybrid phase detector for reduced lock time and timing jitter of phase-locked loops

2008 ◽  
Vol 56 (3) ◽  
pp. 233-240 ◽  
Author(s):  
Jiwang Li ◽  
Fei Yuan
2014 ◽  
Vol 23 (01) ◽  
pp. 1450008
Author(s):  
MARCONI O. DE ALMEIDA ◽  
EDUARDO T. F. SANTOS ◽  
JOSÉ M. ARAÚJO

Phase-locked loops (PLL) is a phase and/or frequency tracking system, widely used in communication and control systems. The sinusoidal multiplicative type PLL still remains a recurrent model, due the fact that its derivation is originated from the maximum likelihood approach. In this note, it is showed as a generalized product, called q-product, which can be used to implement the phase detector and improve some important parameters of the PLL system, as the block linearity and pull-in characteristics. Numerical examples are presented in order to illustrate the proposal.


2008 ◽  
Vol 44 (12) ◽  
pp. 758 ◽  
Author(s):  
L. Naglič ◽  
L. Pavlovič ◽  
B. Batagelj ◽  
M. Vidmar

Author(s):  
M. M. Gourary ◽  
S. G. Rusakov ◽  
S. L. Ulyanov ◽  
M. M. Zharov ◽  
K. K. Gullapalli ◽  
...  

2010 ◽  
Vol 8 ◽  
pp. 161-166 ◽  
Author(s):  
C. Wiegand ◽  
C. Hedayat ◽  
U. Hilleringmann

Abstract. The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete linear model neglecting its non-linear switching behaviour. I.e., the time-varying model is approximated by a time-invariant representation using its average dynamics. Depending on what kind of phase detector is used, the scopes of validity of these approximations are different. Here, a preeminent characterization and simulation technique based on the systems event-driven feature is presented, merging the logical and analogue inherent characteristics of the system. In particular, the high-grade non-linear locking process and the dead-zone are analyzed.


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